URL
https://opencores.org/ocsvn/de1_olpcl2294_system/de1_olpcl2294_system/trunk
Show entire file |
Details |
Blame |
View Log
Rev 8 |
Rev 10 |
Line 17... |
Line 17... |
output sys_err_o,
|
output sys_err_o,
|
output sys_rty_o,
|
output sys_rty_o,
|
|
|
input async_rst_i,
|
input async_rst_i,
|
|
|
|
output reg sys_audio_clk_en,
|
|
|
output [6:0] hex0,
|
output [6:0] hex0,
|
output [6:0] hex1,
|
output [6:0] hex1,
|
output [6:0] hex2,
|
output [6:0] hex2,
|
output [6:0] hex3,
|
output [6:0] hex3,
|
|
|
Line 49... |
Line 51... |
if( sys_rst_o )
|
if( sys_rst_o )
|
sys_rst_r <= 1'h0;
|
sys_rst_r <= 1'h0;
|
else if( (sys_cyc_i & sys_stb_i & sys_we_i) & (register_offset_r == 4'h0) )
|
else if( (sys_cyc_i & sys_stb_i & sys_we_i) & (register_offset_r == 4'h0) )
|
sys_rst_r <= sys_data_i[0];
|
sys_rst_r <= sys_data_i[0];
|
|
|
wire [31:0] sys_register_0 = { 31'b0, sys_rst_r };
|
always @( posedge sys_clk_i )
|
|
if( sys_rst_o )
|
|
sys_audio_clk_en <= 1'h0;
|
|
else if( (sys_cyc_i & sys_stb_i & sys_we_i) & (register_offset_r == 4'h0) )
|
|
sys_audio_clk_en <= sys_data_i[4];
|
|
|
|
wire [31:0] sys_register_0 = {
|
|
27'b0,
|
|
sys_audio_clk_en,
|
|
3'b000,
|
|
sys_rst_r
|
|
};
|
|
|
|
|
//---------------------------------------------------
|
//---------------------------------------------------
|
// register offset 0x4 -- hex led display register
|
// register offset 0x4 -- hex led display register
|
reg [31:0] sys_register_4;
|
reg [31:0] sys_register_4;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.