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Release 13.1 par O.40d (nt)
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Release 13.1 par O.40d (nt)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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DEVELOP-W7:: Thu Aug 11 00:07:18 2011
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DEVELOP-W7:: Thu Aug 11 21:31:46 2011
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par -w -intstyle ise -ol high -xe n -mt 4 debounce_atlys_top_map.ncd
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par -w -intstyle ise -ol high -xe n -mt 4 debounce_atlys_top_map.ncd
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debounce_atlys_top.ncd debounce_atlys_top.pcf
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debounce_atlys_top.ncd debounce_atlys_top.pcf
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Line 25... |
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Device Utilization Summary:
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Device Utilization Summary:
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Slice Logic Utilization:
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Slice Logic Utilization:
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Number of Slice Registers: 46 out of 54,576 1%
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Number of Slice Registers: 42 out of 54,576 1%
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Number used as Flip Flops: 46
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Number used as Flip Flops: 42
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Number used as Latches: 0
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 43 out of 27,288 1%
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Number of Slice LUTs: 37 out of 27,288 1%
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Number used as logic: 38 out of 27,288 1%
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Number used as logic: 36 out of 27,288 1%
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Number using O6 output only: 18
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Number using O6 output only: 18
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Number using O5 output only: 12
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Number using O5 output only: 11
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Number using O5 and O6: 8
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Number using O5 and O6: 7
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Number used as ROM: 0
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Number used as ROM: 0
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Number used as Memory: 0 out of 6,408 0%
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Number used as Memory: 0 out of 6,408 0%
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Number used exclusively as route-thrus: 5
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Number used exclusively as route-thrus: 1
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Number with same-slice register load: 4
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Number with same-slice register load: 0
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Number with same-slice carry load: 1
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Number with same-slice carry load: 1
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Number with other load: 0
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Number with other load: 0
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Slice Logic Distribution:
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Slice Logic Distribution:
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Number of occupied Slices: 17 out of 6,822 1%
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Number of occupied Slices: 19 out of 6,822 1%
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Number of LUT Flip Flop pairs used: 57
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Number of LUT Flip Flop pairs used: 56
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Number with an unused Flip Flop: 21 out of 57 36%
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Number with an unused Flip Flop: 20 out of 56 35%
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Number with an unused LUT: 14 out of 57 24%
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Number with an unused LUT: 19 out of 56 33%
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Number of fully used LUT-FF pairs: 22 out of 57 38%
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Number of fully used LUT-FF pairs: 17 out of 56 30%
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Number of slice register sites lost
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Number of slice register sites lost
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to control set restrictions: 0 out of 54,576 0%
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to control set restrictions: 0 out of 54,576 0%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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IO Utilization:
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Number of bonded IOBs: 34 out of 218 15%
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Number of bonded IOBs: 31 out of 218 14%
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Number of LOCed IOBs: 34 out of 34 100%
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Number of LOCed IOBs: 31 out of 31 100%
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Specific Feature Utilization:
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 116 0%
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Number of RAMB16BWERs: 0 out of 116 0%
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Number of RAMB8BWERs: 0 out of 232 0%
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Number of RAMB8BWERs: 0 out of 232 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Finished initial Timing Analysis. REAL time: 4 secs
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Finished initial Timing Analysis. REAL time: 4 secs
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Starting Router
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Starting Router
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Phase 1 : 231 unrouted; REAL time: 5 secs
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Phase 1 : 199 unrouted; REAL time: 5 secs
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Phase 2 : 199 unrouted; REAL time: 5 secs
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Phase 2 : 168 unrouted; REAL time: 5 secs
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Phase 3 : 51 unrouted; REAL time: 6 secs
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Phase 3 : 46 unrouted; REAL time: 6 secs
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Phase 4 : 51 unrouted; (Par is working to improve performance) REAL time: 7 secs
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Phase 4 : 46 unrouted; (Par is working to improve performance) REAL time: 7 secs
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Updating file: debounce_atlys_top.ncd with current fully routed design.
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Updating file: debounce_atlys_top.ncd with current fully routed design.
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Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
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Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
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Line 140... |
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net gcl | SETUP | N/A| 4.464ns| N/A| 0
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Autotimespec constraint for clock net gcl | SETUP | N/A| 4.423ns| N/A| 0
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k_i_BUFGP | HOLD | 0.388ns| | 0| 0
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k_i_BUFGP | HOLD | 0.424ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------------
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All constraints were met.
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All constraints were met.
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INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
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INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
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All signals are completely routed.
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All signals are completely routed.
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Total REAL time to PAR completion: 8 secs
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Total REAL time to PAR completion: 8 secs
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Total CPU time to PAR completion: 8 secs
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Total CPU time to PAR completion: 8 secs
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Peak Memory Usage: 262 MB
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Peak Memory Usage: 259 MB
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Placer: Placement generated during map.
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of error messages: 0
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