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-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
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-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
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--
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--
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-- Create Date: 01:21:32 06/30/2011
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-- Create Date: 01:21:32 06/30/2011
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-- Design Name:
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-- Design Name:
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-- Module Name: debounce_atlys_top
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-- Module Name: debounce_atlys_top
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-- Project Name: spi_master_slave
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-- Project Name: debounce_vhdl
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-- Target Devices: Spartan-6 LX45
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-- Target Devices: Spartan-6 LX45
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-- Tool versions: ISE 13.1
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-- Tool versions: ISE 13.1
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-- Description:
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-- Description:
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-- This is a verification project for the Digilent Atlys board, to test the SPI_MASTER, SPI_SLAVE and GRP_DEBOUNCE cores.
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-- This is a verification project for the Digilent Atlys board, to test the GRP_DEBOUNCE core.
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-- It uses the board's 100MHz clock input, and clocks all sequential logic at this clock.
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-- It uses the board's 100MHz clock input, and clocks all sequential logic at this clock.
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--
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--
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-- See the "spi_master_atlys.ucf" file for pin assignments.
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-- See the "debounce_atlys.ucf" file for pin assignments.
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-- The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
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-- The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
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-- with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
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-- with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
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-- digital pod port.
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-- digital pod port.
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--
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--
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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-- external monitoring pins to the VHDCI ports.
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-- external monitoring pins to the VHDCI ports.
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-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
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-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
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-- 6.25MHz, 1MHz and 500kHz
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-- 6.25MHz, 1MHz and 500kHz
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-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
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-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
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-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
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-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
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-- 2011/08/10 v1.01.0025 [JD] changed to test the grp_debouncer.vhd module alone.
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--
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--
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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