| Line 38... |
Line 38... |
-- | /------))___/ )OR |-----/ |
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-- | /------))___/ )OR |-----/ |
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-- | | /---)___/ |
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-- | | /---)___/ |
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-- | | | |
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-- | | | |
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-- | | \----------\ |
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-- | | \----------\ |
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-- | | N | |
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-- | | N | |
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-- | \--------/-----------\ +----------------------+-----------\
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-- | \--------/-----------\ +----------------------+---------\
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-- | | | |
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-- | | | |
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-- \---\ | | |
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-- \---\ | | |
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-- ______ | ______ | | ______ |
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-- ______ | ______ | | ______ |
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-- | fd | | | fd | | | |fde | |
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-- | fd | | | fd | | | |fde | |
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-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-------------)----------------------[data_o]
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-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-----------)------------------------[data_o]
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-- N | | N N | | N | | | | N | N |
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-- N | | N N | | N | | | | N | N |
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-- | | | | | \---|CE | | |
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-- | | | | | \---|CE | | |
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-- | | | | | | | | |
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-- | | | | | | | | |
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-- [clk_i]----> |> | |> | | |> | | | ____
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-- [clk_i]----> |> | |> | | |> | | | ____ ______
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-- ------ ------ | ------ | N ____ \-----| \
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-- ------ ------ | ------ | N ____ \---| \ | fd |
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-- | \----/----)) \ |AND |-----------[strb_o]
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-- | \---/---)) \ |AND |-----| |----[strb_o]
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-- | ))XOR |-------|___/
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-- | ))XOR |-----|___/ | |
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-- \--------------------------/----))___/
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-- \-------------------------/---))___/ | |
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-- N
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-- N | |
|
|
-- |> |
|
|
-- ------
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--
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--
|
--
|
--
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-- PIPELINE LOGIC
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-- PIPELINE LOGIC
|
-- ==============
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-- ==============
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--
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--
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| Line 73... |
Line 75... |
-- behaviour of the selected signals.
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-- behaviour of the selected signals.
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--
|
--
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-- RESOURCES USED
|
-- RESOURCES USED
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-- ==============
|
-- ==============
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--
|
--
|
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers.
|
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) + 1 registers.
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-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2.
|
-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2.
|
-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r.
|
-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r.
|
--
|
--
|
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
|
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
|
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i.
|
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clock.
|
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
|
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
|
--
|
--
|
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
|
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
|
--
|
--
|
--
|
--
|
| Line 108... |
Line 110... |
--
|
--
|
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
|
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
|
--
|
--
|
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference.
|
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference.
|
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45).
|
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45).
|
|
-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output.
|
--
|
--
|
-----------------------------------------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------------------------------------
|
-- TODO
|
-- TODO
|
-- ====
|
-- ====
|
--
|
--
|
| Line 136... |
Line 139... |
architecture rtl of grp_debouncer is
|
architecture rtl of grp_debouncer is
|
-- datapath pipeline
|
-- datapath pipeline
|
signal reg_A, reg_B : std_logic_vector (N-1 downto 0) := (others => '0'); -- debounce edge detectors
|
signal reg_A, reg_B : std_logic_vector (N-1 downto 0) := (others => '0'); -- debounce edge detectors
|
signal reg_out : std_logic_vector (N-1 downto 0) := (others => '0'); -- registered output
|
signal reg_out : std_logic_vector (N-1 downto 0) := (others => '0'); -- registered output
|
signal dat_strb : std_logic := '0'; -- data transfer strobe
|
signal dat_strb : std_logic := '0'; -- data transfer strobe
|
|
signal strb_reg : std_logic := '0'; -- registered strobe
|
|
signal strb_next : std_logic := '0'; -- lookahead strobe
|
signal dat_diff : std_logic := '0'; -- edge detector
|
signal dat_diff : std_logic := '0'; -- edge detector
|
-- debounce counter
|
-- debounce counter
|
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter
|
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter
|
signal cnt_next : integer range CNT_VAL downto 0 := 0; -- combinatorial signal
|
signal cnt_next : integer range CNT_VAL downto 0 := 0; -- combinatorial signal
|
begin
|
begin
|
| Line 167... |
Line 172... |
-- DATAPATH SIGNAL PIPELINE
|
-- DATAPATH SIGNAL PIPELINE
|
--=============================================================================================
|
--=============================================================================================
|
-- input pipeline logic
|
-- input pipeline logic
|
pipeline_proc: process (clk_i) is
|
pipeline_proc: process (clk_i) is
|
begin
|
begin
|
-- edge detection pipeline
|
|
if clk_i'event and clk_i = '1' then
|
if clk_i'event and clk_i = '1' then
|
|
-- edge detection pipeline
|
reg_A <= data_i;
|
reg_A <= data_i;
|
reg_B <= reg_A;
|
reg_B <= reg_A;
|
|
-- new data strobe pipeline delay
|
|
strb_reg <= strb_next;
|
end if;
|
end if;
|
|
-- output data pipeline
|
if clk_i'event and clk_i = '1' then
|
if clk_i'event and clk_i = '1' then
|
if dat_strb = '1' then
|
if dat_strb = '1' then
|
reg_out <= reg_B;
|
reg_out <= reg_B;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process pipeline_proc;
|
end process pipeline_proc;
|
-- edge detector
|
-- edge detector
|
edge_detector_proc: dat_diff <= '1' when reg_A /= reg_B else '0';
|
edge_detector_proc: dat_diff <= '1' when reg_A /= reg_B else '0';
|
|
-- lookahead new data strobe
|
|
next_strobe_proc: strb_next <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0';
|
|
|
--=============================================================================================
|
--=============================================================================================
|
-- OUTPUT LOGIC
|
-- OUTPUT LOGIC
|
--=============================================================================================
|
--=============================================================================================
|
-- new data strobe detection
|
|
strb_o_proc: strb_o <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0';
|
|
-- connect output ports
|
-- connect output ports
|
data_o_proc: data_o <= reg_out;
|
data_o_proc: data_o <= reg_out;
|
|
strb_o_proc: strb_o <= strb_reg;
|
end rtl;
|
end rtl;
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
