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VHDL files for spi master/slave project:
VHDL files for spi master/slave project:
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grp_debouncer.vhd       switch debouncer model
grp_debouncer.vhd       switch debouncer model
grp_debouncer_test.vhd  testbench for simulating the switch debouncer model
 
 
 
 
 
The original development is done in Xilinx ISE 13.1, targeted to a Spartan-6 device.
The original development is done in Xilinx ISE 13.1, targeted to a Spartan-6 device.
 
 
ISIM SIMULATION
ISIM SIMULATION

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