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-- Create Date: Open source, from 12c core hosted at www.opencores.org
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-- Design Name:
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-- Module Name: Log function base 2
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-- Project Name: Deflate
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-- Target Device:
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-- Dependencies:
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--
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-- Revision: NA
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-- Additional Comments:
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-- Use this to convert the memeory lengths to the 2^x values
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-- to dynamically assign the widths of the address
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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--Function to find the log of a number
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--Is used to convert the addresses
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package mat is
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function log2(v: in natural) return natural;
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end package mat;
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--Function definition
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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package body mat is
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function log2(v: in natural) return natural is
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variable n: natural;
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variable logn: natural;
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begin
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n := 1;
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for i in 0 to 128 loop
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logn := i;
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exit when (n>=v);
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n := n * 2;
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end loop;
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return logn;
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end function log2;
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end package body mat;
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--End of the package
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--------------------------------------------------------------------------------
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-- Create Date: 17:24:38 20/05/2006
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-- Design Name:
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-- Module Name:
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-- Project Name: Deflate
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-- Target Device:
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-- Dependencies: hahskey.vhdl
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--
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-- Revision:
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-- Revision 0.50 - Works but not optimised
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-- Additional Comments:
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-- This componenet controls the data input and stores the data alongwith
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-- the source in 32k buffers ,
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-- It recieves the data directly and then on finding a minimum match
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-- Drives its match output high along with the match address on the address output
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-- and the current offset on the next clock cycle
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-- waits for the next +ve edge on the Active data input
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-- to go high before resuming, the output/ input is +ve edge triggered
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.mat.all;
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entity input_process is
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Generic
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(
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-- Number of bits in the key
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Hash_Width : natural := 32;
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-- Data bus width
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Data_Width : natural := 8;
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-- Buffer allocated to the hash table and the source buffer = 32k tables
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-- The key buffer has to be equal to the Hash_Width above and
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-- the source buffer of Dat width
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-- Start address for the memory bank at which the hash keys need to be stored
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-- The end address is calculated by adding the length of the table to that address
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Length_of_Table : natural := 32768
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);
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Port
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(
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--Outputs to read/write the key values.
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hash_tbl_dat : inout std_logic_vector ( Hash_Width - 1 downto 0);
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--Port to read/write data values
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source_buff_dat : inout std_logic_vector ( Data_Width - 1 downto 0);
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-- Matching 4 bytes fond for the last 4 inputs
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Match,
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-- Ready for crunching
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Ready,
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-- The sync signals to the memory, read write operations
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-- done simultaneously on both memry banks
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-- The design will currently work with SRAM and will need a wrapper to
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-- work with DRAM
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-- Active data on output
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Act_data_out,
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--Read or write operation 0 = read, 1 = write
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RW : out bit ;
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-- Current address in buffers
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Curr_addres : out std_logic_vector (log2 ( Length_of_Table ) - 1 downto 0);
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--******
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--Input signals
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--Data in
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source_dat : inout std_logic_vector ( Data_Width - 1 downto 0);
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-- Input Data Clock
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Act_dat,
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-- Clock
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Src_clk,
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-- Reset
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Reset : in bit
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);
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end input_process;
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architecture mealy_machine of input_process is
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component hash_key is
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generic
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(
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hash_width: natural := 32;
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data_width: natural := 8);
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port
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(
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data_in: in std_logic_vector(data_width -1 downto 0);
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hash_out: out std_logic_vector (hash_width -1 downto 0);
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Clock,
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reset,
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start : in bit;
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ready,
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busy: out bit);
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end component;
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-- Buffer address start for the key table
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Signal key_address,
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buffer_address: std_logic_vector (log2 ( Length_of_Table ) - 1 downto 0);
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-- Accept a 32 bit hash input
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signal hg1: std_logic_vector ( (Hash_Width -1) downto 0);
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-- 8 bit io buffer
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signal Buffer_1 : std_logic_vector (Data_Width-1 downto 0);
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--Component signals from the key algorithm
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signal Algo_start,
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Algo_clk,
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Algo_rst,
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Algo_op,
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Algo_bsy, -- Algorithm sync aignals
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Search_done,
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Busy,
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red_rst,
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red_opr,
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val_match: bit := '0'; --Internal sync sgnals
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signal mode,
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store_count :integer;
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begin
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--Unlike the sub components this module has a slightly complex reset cycle
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--It resets the offset counters to 0, uses the next 7 clock cyces to read the
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--start addresses for the data and key buffer
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resetter: process (Src_Clk)
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variable tmp: integer;
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variable red: bit :='0';
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Begin
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if Src_Clk'event and Src_Clk = '1' then
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if mode /= 0 then
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red_rst <= '0';
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tmp := 0;
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else
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case tmp is
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when 0 =>
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buffer_address (7 downto 0) <= source_dat;
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when 1 =>
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buffer_address (14 downto 8) <= source_dat (6 downto 0);
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when 2 =>
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key_address (7 downto 0) <= source_dat;
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when 3 =>
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key_address (14 downto 8) <= source_dat (6 downto 0);
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when 4 =>
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red_rst <= '1';
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when others =>
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red_rst <= '0';
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end case;
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end if;
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end if;
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end process resetter;
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--The main input mealy machine is defined below
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-- It has 6 states of operation
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-- Mode 0 : Reset
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-- Mode 1 : Wait
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-- Mode 2 : Active data input generationg a key for it and the last 3 bytes
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-- Mode 3 : Storing the key and the input data
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-- Mode 4 : Searching the hash buffer for a 4 byte match
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-- Mode 5 : Match found, on the next clock cycle output current buffer offet
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-- and on the second clock cycle output the match offset
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input_control : process (Act_dat, Src_Clk, Reset )
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begin
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--+ Ve edge triggered
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if Src_Clk'event and Src_Clk = '1' then
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-- Mealy machine
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If Reset = '1' or ( mode = 0 and red_rst ='0' ) then
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mode <= 0;
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elsif mode < 2 and Act_dat = '1' then
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mode <= 2;
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elsif mode = 2 and Algo_bsy = '0' and store_count < 3 then
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mode <= 3;
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elsif mode = 2 and Algo_bsy = '0' then
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mode <= 4;
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elsif mode = 4 and Search_done = '1' and val_match = '1' then
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mode <= 5;
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elsif mode = 4 and Search_done = '1' then
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mode <= 3;
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elsif ( mode = 5 or mode = 3 ) and Busy = '0' then
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mode <= 1;
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else
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mode <= mode;
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end if;
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end if;
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end process input_control;
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--************************************************
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-- Algorithm component addition
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Key_Gen: hash_key port map
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(
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data_in => Buffer_1,
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hash_out => hg1,
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Clock => Algo_clk,
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reset => Algo_rst,
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start => Algo_start,
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ready => Algo_op,
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busy => Algo_bsy
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);
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-- ************************************************
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Ready <= red_rst or red_opr;
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end mealy_machine;
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