URL https://opencores.org/ocsvn/des/des/trunk

Subversion Repositories des

[/] [des/] [trunk/] [rtl/] [verilog/] [perf_opt/] [des.v] - Diff between revs 5 and 7

Rev 5	Rev 7
Line 206...	Line 206...

`// 32 bit R15 gets 32 bit L14 XOR'd with 32 bit out15`	`// 32 bit R15 gets 32 bit L14 XOR'd with 32 bit out15`
`always @(posedge clk)`	`always @(posedge clk)`
`R15 <= #1 L14 ^ out15;`	`R15 <= #1 L14 ^ out15;`


`// Perform the initial permutationi with the registerd desIn`	`// Perform the initial permutationi with the registerd desIn`
`assign IP[1:64] = { desIn_r[06], desIn_r[14], desIn_r[22], desIn_r[30], desIn_r[38], desIn_r[46],`	`assign IP[1:64] = { desIn_r[06], desIn_r[14], desIn_r[22], desIn_r[30], desIn_r[38], desIn_r[46],`
`desIn_r[54], desIn_r[62], desIn_r[04], desIn_r[12], desIn_r[20], desIn_r[28],`	`desIn_r[54], desIn_r[62], desIn_r[04], desIn_r[12], desIn_r[20], desIn_r[28],`
`desIn_r[36], desIn_r[44], desIn_r[52], desIn_r[60], desIn_r[02], desIn_r[10],`	`desIn_r[36], desIn_r[44], desIn_r[52], desIn_r[60], desIn_r[02], desIn_r[10],`
`desIn_r[18], desIn_r[26], desIn_r[34], desIn_r[42], desIn_r[50], desIn_r[58],`	`desIn_r[18], desIn_r[26], desIn_r[34], desIn_r[42], desIn_r[50], desIn_r[58],`