| Line 1... |
Line 1... |
Release 7.1.04i - xst H.42
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Release 7.1.04i - xst H.42
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Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to __projnav
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--> Parameter TMPDIR set to __projnav
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CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
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CPU : 0.00 / 2.52 s | Elapsed : 0.00 / 2.00 s
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--> Parameter xsthdpdir set to ./xst
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--> Parameter xsthdpdir set to ./xst
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CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
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CPU : 0.00 / 2.52 s | Elapsed : 0.00 / 2.00 s
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--> Reading design: updater.prj
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--> Reading design: updater.prj
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TABLE OF CONTENTS
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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1) Synthesis Options Summary
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| Line 30... |
Line 30... |
Ignore Synthesis Constraint File : NO
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Ignore Synthesis Constraint File : NO
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|
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---- Target Parameters
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---- Target Parameters
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Output File Name : "updater"
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Output File Name : "updater"
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Output Format : NGC
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Output Format : NGC
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Target Device : xc2v250-6-cs144
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Target Device : xc2v2000-6-bg575
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|
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---- Source Options
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---- Source Options
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Top Module Name : updater
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Top Module Name : updater
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Automatic FSM Extraction : YES
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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FSM Encoding Algorithm : Auto
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| Line 63... |
Line 63... |
Slice Packing : YES
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Slice Packing : YES
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Pack IO Registers into IOBs : auto
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Pack IO Registers into IOBs : auto
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|
|
---- General Options
|
---- General Options
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Optimization Goal : Speed
|
Optimization Goal : Speed
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Optimization Effort : 1
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Optimization Effort : 2
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Keep Hierarchy : NO
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Keep Hierarchy : NO
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Global Optimization : AllClockNets
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Global Optimization : AllClockNets
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RTL Output : Yes
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RTL Output : Yes
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Write Timing Constraints : NO
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Write Timing Constraints : NO
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Hierarchy Separator : _
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Hierarchy Separator : _
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| Line 93... |
Line 93... |
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=========================================================================
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=========================================================================
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* HDL Compilation *
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* HDL Compilation *
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=========================================================================
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=========================================================================
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Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd" in Library work.
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Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd" in Library work.
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Architecture rtl of Entity updater is up to date.
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Entity compiled.
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Entity (Architecture ) compiled.
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|
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=========================================================================
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=========================================================================
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* HDL Analysis *
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* HDL Analysis *
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=========================================================================
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=========================================================================
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Analyzing Entity (Architecture ).
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Analyzing Entity (Architecture ).
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| Line 108... |
Line 109... |
=========================================================================
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=========================================================================
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* HDL Synthesis *
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* HDL Synthesis *
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=========================================================================
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=========================================================================
|
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Synthesizing Unit .
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Synthesizing Unit .
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Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd".
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Related source file is "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd".
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WARNING:Xst:1780 - Signal is never used or assigned.
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Found 8-bit 4-to-1 multiplexer for signal .
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Found 10-bit 4-to-1 multiplexer for signal .
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Found 8-bit 4-to-1 multiplexer for signal .
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Found 10-bit 4-to-1 multiplexer for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 10-bit adder for signal <$n0009> created at line 51.
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Found 8-bit adder for signal <$n0009> created at line 50.
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Found 10-bit adder for signal <$n0011> created at line 73.
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Found 8-bit adder for signal <$n0011> created at line 72.
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Found 10-bit adder for signal <$n0012> created at line 84.
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Found 8-bit adder for signal <$n0012> created at line 83.
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Found 10-bit adder for signal <$n0013> created at line 62.
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Found 8-bit adder for signal <$n0013> created at line 61.
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Found 10-bit register for signal .
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Found 8-bit register for signal .
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Found 10-bit register for signal .
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Found 8-bit register for signal .
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Found 10-bit register for signal .
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Found 8-bit register for signal .
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Found 10-bit register for signal .
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Found 8-bit register for signal .
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Found 10-bit register for signal .
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Found 8-bit register for signal .
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Found 1-bit xor2 for signal .
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Found 1-bit xor2 for signal .
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Summary:
|
Summary:
|
inferred 1 D-type flip-flop(s).
|
inferred 1 D-type flip-flop(s).
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inferred 4 Adder/Subtractor(s).
|
inferred 4 Adder/Subtractor(s).
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inferred 20 Multiplexer(s).
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inferred 16 Multiplexer(s).
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Unit synthesized.
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Unit synthesized.
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|
|
|
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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* Advanced HDL Synthesis *
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| Line 144... |
Line 144... |
=========================================================================
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=========================================================================
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HDL Synthesis Report
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HDL Synthesis Report
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|
|
Macro Statistics
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Macro Statistics
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# Adders/Subtractors : 4
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# Adders/Subtractors : 4
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10-bit adder : 4
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8-bit adder : 4
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# Registers : 6
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# Registers : 6
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1-bit register : 1
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1-bit register : 1
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10-bit register : 5
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8-bit register : 5
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# Multiplexers : 2
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# Multiplexers : 2
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10-bit 4-to-1 multiplexer : 2
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8-bit 4-to-1 multiplexer : 2
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# Xors : 1
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# Xors : 1
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1-bit xor2 : 1
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1-bit xor2 : 1
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|
|
=========================================================================
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=========================================================================
|
|
|
=========================================================================
|
=========================================================================
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* Low Level Synthesis *
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* Low Level Synthesis *
|
=========================================================================
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=========================================================================
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|
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Optimizing unit ...
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Optimizing unit ...
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Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx.
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Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.
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Mapping all equations...
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Mapping all equations...
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Building and optimizing final netlist ...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block updater, actual ratio is 2.
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Found area constraint ratio of 100 (+ 5) on block updater, actual ratio is 0.
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|
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=========================================================================
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=========================================================================
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* Final Report *
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* Final Report *
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=========================================================================
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=========================================================================
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Final Results
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Final Results
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| Line 177... |
Line 177... |
Output Format : NGC
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Output Format : NGC
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Optimization Goal : Speed
|
Optimization Goal : Speed
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Keep Hierarchy : NO
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Keep Hierarchy : NO
|
|
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Design Statistics
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Design Statistics
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# IOs : 45
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# IOs : 37
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|
|
Macro Statistics :
|
Macro Statistics :
|
# Registers : 51
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# Registers : 41
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# 1-bit register : 51
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# 1-bit register : 41
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# Multiplexers : 2
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# Multiplexers : 2
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# 10-bit 4-to-1 multiplexer : 2
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# 8-bit 4-to-1 multiplexer : 2
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# Adders/Subtractors : 4
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# Adders/Subtractors : 4
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# 10-bit adder : 4
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# 8-bit adder : 4
|
|
|
Cell Usage :
|
Cell Usage :
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# BELS : 155
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# BELS : 123
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# GND : 1
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# GND : 1
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# INV : 3
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# INV : 3
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# LUT1 : 35
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# LUT1 : 27
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# LUT2 : 9
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# LUT2 : 2
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# LUT3 : 20
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# LUT3 : 6
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# LUT4 : 5
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# LUT4 : 20
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# MUXCY : 36
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# MUXCY : 28
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# MUXF5 : 10
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# MUXF5 : 8
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# VCC : 1
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# VCC : 1
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# XORCY : 35
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# XORCY : 27
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# FlipFlops/Latches : 51
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# FlipFlops/Latches : 41
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# FDR : 46
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# FDR : 36
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# FDS : 5
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# FDS : 5
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# Clock Buffers : 1
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# Clock Buffers : 1
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# BUFGP : 1
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# BUFGP : 1
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# IO Buffers : 44
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# IO Buffers : 36
|
# IBUF : 23
|
# IBUF : 19
|
# OBUF : 21
|
# OBUF : 17
|
=========================================================================
|
=========================================================================
|
|
|
Device utilization summary:
|
Device utilization summary:
|
---------------------------
|
---------------------------
|
|
|
Selected Device : 2v250cs144-6
|
Selected Device : 2v2000bg575-6
|
|
|
Number of Slices: 40 out of 1536 2%
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Number of Slices: 32 out of 10752 0%
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Number of Slice Flip Flops: 51 out of 3072 1%
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Number of Slice Flip Flops: 41 out of 21504 0%
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Number of 4 input LUTs: 69 out of 3072 2%
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Number of 4 input LUTs: 55 out of 21504 0%
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Number of bonded IOBs: 45 out of 92 48%
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Number of bonded IOBs: 37 out of 408 9%
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Number of GCLKs: 1 out of 16 6%
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Number of GCLKs: 1 out of 16 6%
|
|
|
|
|
=========================================================================
|
=========================================================================
|
TIMING REPORT
|
TIMING REPORT
|
| Line 233... |
Line 233... |
Clock Information:
|
Clock Information:
|
------------------
|
------------------
|
-----------------------------------+------------------------+-------+
|
-----------------------------------+------------------------+-------+
|
Clock Signal | Clock buffer(FF name) | Load |
|
Clock Signal | Clock buffer(FF name) | Load |
|
-----------------------------------+------------------------+-------+
|
-----------------------------------+------------------------+-------+
|
CLOCK | BUFGP | 51 |
|
CLOCK | BUFGP | 41 |
|
-----------------------------------+------------------------+-------+
|
-----------------------------------+------------------------+-------+
|
|
|
Timing Summary:
|
Timing Summary:
|
---------------
|
---------------
|
Speed Grade: -6
|
Speed Grade: -6
|
|
|
Minimum period: No path found
|
Minimum period: No path found
|
Minimum input arrival time before clock: 5.514ns
|
Minimum input arrival time before clock: 5.430ns
|
Maximum output required time after clock: 5.814ns
|
Maximum output required time after clock: 5.814ns
|
Maximum combinational path delay: 8.733ns
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Maximum combinational path delay: 8.314ns
|
|
|
Timing Detail:
|
Timing Detail:
|
--------------
|
--------------
|
All values displayed in nanoseconds (ns)
|
All values displayed in nanoseconds (ns)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
|
Total number of paths / destination ports: 464 / 102
|
Total number of paths / destination ports: 291 / 82
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 5.514ns (Levels of Logic = 13)
|
Offset: 5.430ns (Levels of Logic = 11)
|
Source: NUMERATOR<2> (PAD)
|
Source: NUMERATOR<2> (PAD)
|
Destination: NUMERATOR4_9 (FF)
|
Destination: NUMERATOR4_7 (FF)
|
Destination Clock: CLOCK rising
|
Destination Clock: CLOCK rising
|
|
|
Data Path: NUMERATOR<2> to NUMERATOR4_9
|
Data Path: NUMERATOR<2> to NUMERATOR4_7
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
IBUF:I->O 3 0.653 0.760 NUMERATOR_2_IBUF (NUMERATOR_2_IBUF)
|
IBUF:I->O 3 0.653 0.760 NUMERATOR_2_IBUF (NUMERATOR_2_IBUF)
|
LUT1:I0->O 1 0.347 0.000 NUMERATOR_2_IBUF_rt1 (NUMERATOR_2_IBUF_rt1)
|
LUT1:I0->O 1 0.347 0.000 NUMERATOR_2_IBUF_rt1 (NUMERATOR_2_IBUF_rt1)
|
MUXCY:S->O 1 0.235 0.000 updater__n0013<1>cy (updater__n0013<1>_cyo)
|
MUXCY:S->O 1 0.235 0.000 updater__n0013<1>cy (updater__n0013<1>_cyo)
|
MUXCY:CI->O 1 0.042 0.000 updater__n0013<2>cy (updater__n0013<2>_cyo)
|
MUXCY:CI->O 1 0.042 0.000 updater__n0013<2>cy (updater__n0013<2>_cyo)
|
MUXCY:CI->O 1 0.042 0.000 updater__n0013<3>cy (updater__n0013<3>_cyo)
|
MUXCY:CI->O 1 0.042 0.000 updater__n0013<3>cy (updater__n0013<3>_cyo)
|
MUXCY:CI->O 1 0.042 0.000 updater__n0013<4>cy (updater__n0013<4>_cyo)
|
MUXCY:CI->O 1 0.042 0.000 updater__n0013<4>cy (updater__n0013<4>_cyo)
|
MUXCY:CI->O 1 0.042 0.000 updater__n0013<5>cy (updater__n0013<5>_cyo)
|
MUXCY:CI->O 1 0.042 0.000 updater__n0013<5>cy (updater__n0013<5>_cyo)
|
MUXCY:CI->O 1 0.042 0.000 updater__n0013<6>cy (updater__n0013<6>_cyo)
|
XORCY:CI->O 2 0.824 0.744 updater__n0013<6>_xor (_n0013<6>)
|
MUXCY:CI->O 1 0.042 0.000 updater__n0013<7>cy (updater__n0013<7>_cyo)
|
LUT1:I0->O 1 0.347 0.000 _n0013<6>_rt (_n0013<6>_rt)
|
XORCY:CI->O 2 0.824 0.744 updater__n0013<8>_xor (_n0013<8>)
|
MUXCY:S->O 0 0.235 0.000 updater__n0011<6>cy (updater__n0011<6>_cyo)
|
LUT1:I0->O 1 0.347 0.000 _n0013<8>_rt (_n0013<8>_rt)
|
XORCY:CI->O 1 0.824 0.000 updater__n0011<7>_xor (_n0011<7>)
|
MUXCY:S->O 0 0.235 0.000 updater__n0011<8>cy (updater__n0011<8>_cyo)
|
FDR:D 0.293 NUMERATOR4_7
|
XORCY:CI->O 1 0.824 0.000 updater__n0011<9>_xor (_n0011<9>)
|
|
FDR:D 0.293 NUMERATOR4_9
|
|
----------------------------------------
|
----------------------------------------
|
Total 5.514ns (4.010ns logic, 1.504ns route)
|
Total 5.430ns (3.926ns logic, 1.504ns route)
|
(72.7% logic, 27.3% route)
|
(72.3% logic, 27.7% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
|
Total number of paths / destination ports: 51 / 21
|
Total number of paths / destination ports: 41 / 17
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 5.814ns (Levels of Logic = 3)
|
Offset: 5.814ns (Levels of Logic = 3)
|
Source: NUMERATOR2_9 (FF)
|
Source: NUMERATOR2_7 (FF)
|
Destination: NUMERATOR_OUT<9> (PAD)
|
Destination: NUMERATOR_OUT<7> (PAD)
|
Source Clock: CLOCK rising
|
Source Clock: CLOCK rising
|
|
|
Data Path: NUMERATOR2_9 to NUMERATOR_OUT<9>
|
Data Path: NUMERATOR2_7 to NUMERATOR_OUT<7>
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDR:C->Q 1 0.449 0.548 NUMERATOR2_9 (NUMERATOR2_9)
|
FDR:C->Q 1 0.449 0.548 NUMERATOR2_7 (NUMERATOR2_7)
|
LUT3:I1->O 1 0.347 0.000 DATA_IN19 (MUX_BLOCK_N19)
|
LUT4:I1->O 1 0.347 0.000 DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6_F (N25)
|
MUXF5:I0->O 1 0.345 0.383 DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_8 (NUMERATOR_OUT_9_OBUF)
|
MUXF5:I0->O 1 0.345 0.383 DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6 (NUMERATOR_OUT_7_OBUF)
|
OBUF:I->O 3.743 NUMERATOR_OUT_9_OBUF (NUMERATOR_OUT<9>)
|
OBUF:I->O 3.743 NUMERATOR_OUT_7_OBUF (NUMERATOR_OUT<7>)
|
----------------------------------------
|
----------------------------------------
|
Total 5.814ns (4.884ns logic, 0.930ns route)
|
Total 5.814ns (4.884ns logic, 0.930ns route)
|
(84.0% logic, 16.0% route)
|
(84.0% logic, 16.0% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default path analysis
|
Timing constraint: Default path analysis
|
Total number of paths / destination ports: 224 / 20
|
Total number of paths / destination ports: 204 / 16
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Delay: 8.733ns (Levels of Logic = 6)
|
Delay: 8.314ns (Levels of Logic = 5)
|
Source: DENOMINATOR<0> (PAD)
|
Source: DENOMINATOR<0> (PAD)
|
Destination: DENOMINATOR_OUT<9> (PAD)
|
Destination: DENOMINATOR_OUT<1> (PAD)
|
|
|
Data Path: DENOMINATOR<0> to DENOMINATOR_OUT<9>
|
Data Path: DENOMINATOR<0> to DENOMINATOR_OUT<1>
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
IBUF:I->O 2 0.653 0.743 DENOMINATOR_0_IBUF (DENOMINATOR_0_IBUF)
|
IBUF:I->O 2 0.653 0.743 DENOMINATOR_0_IBUF (DENOMINATOR_0_IBUF)
|
LUT4:I0->O 1 0.347 0.415 _n001410 (CHOICE6)
|
LUT4:I0->O 23 0.347 1.007 _n00144 (CHOICE167)
|
LUT4:I3->O 1 0.347 0.415 _n001416_SW0 (N27)
|
LUT2:I0->O 2 0.347 0.744 _n001410 (HALVE_VALUES)
|
LUT4:I3->O 20 0.347 0.994 _n001416 (HALVE_VALUES)
|
LUT4:I0->O 1 0.347 0.383 DENOMINATOR_OUT<1>1 (DENOMINATOR_OUT_1_OBUF)
|
LUT2:I0->O 1 0.347 0.383 DENOMINATOR_OUT<9>1 (DENOMINATOR_OUT_9_OBUF)
|
OBUF:I->O 3.743 DENOMINATOR_OUT_1_OBUF (DENOMINATOR_OUT<1>)
|
OBUF:I->O 3.743 DENOMINATOR_OUT_9_OBUF (DENOMINATOR_OUT<9>)
|
|
----------------------------------------
|
----------------------------------------
|
Total 8.733ns (5.784ns logic, 2.949ns route)
|
Total 8.314ns (5.437ns logic, 2.877ns route)
|
(66.2% logic, 33.8% route)
|
(65.4% logic, 34.6% route)
|
|
|
=========================================================================
|
=========================================================================
|
CPU : 4.88 / 5.23 s | Elapsed : 5.00 / 6.00 s
|
CPU : 6.39 / 8.98 s | Elapsed : 7.00 / 9.00 s
|
|
|
-->
|
-->
|
|
|
Total memory usage is 100604 kilobytes
|
Total memory usage is 121148 kilobytes
|
|
|
Number of errors : 0 ( 0 filtered)
|
Number of errors : 0 ( 0 filtered)
|
Number of warnings : 1 ( 0 filtered)
|
Number of warnings : 0 ( 0 filtered)
|
Number of infos : 0 ( 0 filtered)
|
Number of infos : 0 ( 0 filtered)
|
|
|
