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-- ***** BEGIN LICENSE BLOCK *****
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-- ***** BEGIN LICENSE BLOCK *****
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--
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--
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-- $Id: ARITHMETIC_UNIT.vhd,v 1.3 2005-05-27 16:00:28 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- $Id: ARITHMETIC_UNIT.vhd,v 1.4 2006-10-05 16:17:11 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- *
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-- *
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- *
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-- *
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-- * The contents of this file are subject to the Mozilla Public License
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-- * The contents of this file are subject to the Mozilla Public License
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * The Initial Developer of the Original Code is the British Broadcasting
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-- * The Initial Developer of the Original Code is the British Broadcasting
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-- * Corporation.
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-- * Corporation.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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-- * All Rights Reserved.
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-- * All Rights Reserved.
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-- *
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-- *
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-- * Contributor(s): Peter Bleackley (Original author), Stephan Reichör
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-- * Contributor(s): Peter Bleackley (Original author)
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-- *
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-- *
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-- * Alternatively, the contents of this file may be used under the terms of
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-- * Alternatively, the contents of this file may be used under the terms of
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-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- * the GPL or the LGPL are applicable instead of those above. If you wish to
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-- * the GPL or the LGPL are applicable instead of those above. If you wish to
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-- * or LGPL. If you do not delete the provisions above, a recipient may use
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-- * or LGPL. If you do not delete the provisions above, a recipient may use
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-- * your version of this file under the terms of any one of the MPL, the GPL
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-- * your version of this file under the terms of any one of the MPL, the GPL
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-- * or the LGPL.
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-- * or the LGPL.
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-- * ***** END LICENSE BLOCK ***** */
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-- * ***** END LICENSE BLOCK ***** */
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity ARITHMETIC_UNIT is
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entity ARITHMETIC_UNIT is
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Port ( DIFFERENCE : in std_logic_vector(15 downto 0);
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Port ( DIFFERENCE : in std_logic_vector(15 downto 0);
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PROB : in std_logic_vector(9 downto 0);
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PROB : in std_logic_vector(7 downto 0);
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LOW : in std_logic_vector(15 downto 0);
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LOW : in std_logic_vector(15 downto 0);
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ENABLE : in std_logic;
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ENABLE : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
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DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
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end ARITHMETIC_UNIT;
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end ARITHMETIC_UNIT;
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architecture RTL of ARITHMETIC_UNIT is
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architecture RTL of ARITHMETIC_UNIT is
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signal LOW2 : std_logic_vector(16 downto 0);
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signal LOW2 : std_logic_vector(16 downto 0);
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signal PRODUCT : std_logic_vector (26 downto 0);
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signal PRODUCT : std_logic_vector (24 downto 0);
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signal PRODUCT2 : std_logic_vector (16 downto 0);
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signal PRODUCT2 : std_logic_vector (16 downto 0);
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signal RESULT : std_logic_vector (16 downto 0);
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signal RESULT : std_logic_vector (16 downto 0);
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signal RESULT0 : std_logic_vector (16 downto 0);
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signal RESULT0 : std_logic_vector (16 downto 0);
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signal DIFFERENCE1 : std_logic_vector (16 downto 0);
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signal DIFFERENCE1 : std_logic_vector (16 downto 0);
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signal DIFFERENCE2 : std_logic_vector(16 downto 0);
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signal DIFFERENCE2 : std_logic_vector(16 downto 0);
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signal DIFFERENCE3 : std_logic_vector(16 downto 0);
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signal DIFFERENCE3 : std_logic_vector(16 downto 0);
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signal DIFFERENCE4 : std_logic_vector(16 downto 0);
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signal DIFFERENCE4 : std_logic_vector(16 downto 0);
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signal DELAY1 : std_logic;
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signal DELAY1 : std_logic;
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signal DELAY2 : std_logic;
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-- signal DELAY2 : std_logic;
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signal CALCULATE : std_logic;
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signal CALCULATE : std_logic;
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begin
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begin
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-- The arithmetic
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-- The arithmetic
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DIFFERENCE2 <= ('0' & DIFFERENCE) + "00000000000000001";
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DIFFERENCE2 <= ('0' & DIFFERENCE) + "00000000000000001";
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MULTIPLY : process (CLOCK, DIFFERENCE2, PROB)
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MULTIPLY : process (CLOCK)
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begin
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begin
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if CLOCK'event and CLOCK = '1' then
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if CLOCK'event and CLOCK = '1' then
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if ENABLE = '1' then
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PRODUCT <= DIFFERENCE2 * PROB;
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PRODUCT <= DIFFERENCE2 * PROB;
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end if;
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end if;
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end if;
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end process MULTIPLY;
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end process MULTIPLY;
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PRODUCT2 <= PRODUCT(26 downto 10);
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PRODUCT2 <= PRODUCT(24 downto 8);
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RESULT <= LOW2 + PRODUCT2;
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RESULT <= LOW2 + PRODUCT2;
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RESULT_OUT1 <= RESULT(15 downto 0);
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RESULT_OUT1 <= RESULT(15 downto 0);
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RESULT0 <= (RESULT - "00000000000000001");
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RESULT0 <= (RESULT - "00000000000000001");
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RESULT_OUT0 <= RESULT0(15 downto 0);
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RESULT_OUT0 <= RESULT0(15 downto 0);
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DIFFERENCE3 <= (PRODUCT2 - "00000000000000001");
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DIFFERENCE3 <= (PRODUCT2 - "00000000000000001");
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DIFFERENCE4 <= (DIFFERENCE1 - PRODUCT2);
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DIFFERENCE4 <= (DIFFERENCE1 - PRODUCT2);
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DIFFERENCE_OUT1 <= DIFFERENCE4(15 downto 0);
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DIFFERENCE_OUT1 <= DIFFERENCE4(15 downto 0);
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DIFFERENCE_OUT0 <= DIFFERENCE3(15 downto 0);
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-- Control logic
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-- Control logic
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CALCULATE <= ENABLE and not RESET;
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CALCULATE <= ENABLE and not RESET;
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DATA_LOAD <= DELAY1 and DELAY2;
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DATA_LOAD <= DELAY1;-- and DELAY2;
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-- Sequential control logic
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-- Sequential control logic
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DELAYS: process (CLOCK)
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DELAYS: process (CLOCK)
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begin
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begin
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if CLOCK'event and CLOCK = '1' then
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if CLOCK'event and CLOCK = '1' then
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DELAY1 <= CALCULATE;
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DELAY1 <= CALCULATE;
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DELAY2 <= DELAY1;
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-- DELAY2 <= DELAY1;
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if ENABLE = '1' then
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DIFFERENCE1 <= '0' & DIFFERENCE;
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DIFFERENCE1 <= '0' & DIFFERENCE;
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LOW2 <= '0' & LOW;
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LOW2 <= '0' & LOW;
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DIFFERENCE_OUT0 <= DIFFERENCE3(15 downto 0);
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end if;
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end if;
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end if;
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end process DELAYS;
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end process DELAYS;
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