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-- ***** BEGIN LICENSE BLOCK *****
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-- ***** BEGIN LICENSE BLOCK *****
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--
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--
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-- $Id: CONTEXT_MANAGER.vhd,v 1.1 2005-05-27 16:00:28 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- $Id: CONTEXT_MANAGER.vhd,v 1.2 2006-08-18 14:29:32 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- *
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-- *
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- *
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-- *
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-- * The contents of this file are subject to the Mozilla Public License
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-- * The contents of this file are subject to the Mozilla Public License
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity CONTEXT_MANAGER is
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entity CONTEXT_MANAGER is
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Port ( CONTEXT_NUMBER : in std_logic_vector(5 downto 0);
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Port ( CONTEXT_NUMBER : in std_logic_vector(5 downto 0);
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SET : in std_logic;
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UPDATE : in std_logic;
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DATA_IN : in std_logic;
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HALVECOUNTS : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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PROB : out std_logic_vector(9 downto 0));
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PROB : out std_logic_vector(9 downto 0);
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READY : out std_logic);
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end CONTEXT_MANAGER;
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end CONTEXT_MANAGER;
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architecture RTL of CONTEXT_MANAGER is
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architecture RTL of CONTEXT_MANAGER is
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type MATRIX is array (63 downto 0) of std_logic_vector(9 downto 0);
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signal PROBABILITY : MATRIX := ("1111111111","0011011010","1111000000",
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type MATRIX is array (45 downto 0) of std_logic_vector(19 downto 0);
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"1100110000","0111110000","1001111100","0000010000","0000110011","1100110011",
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signal PROBABILITY : MATRIX;
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"1101110111","0110011010","1000111000","0000001010","0000110011","1000110011",
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constant HALF : std_logic_vector(19 downto 0) := "00000000010000000010";
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"0101011011","1110000000","0100111101","1000001010","1110011011","0000001010",
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signal FRACTION : std_logic_vector(19 downto 0);
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"0101111000","1111000000","1111001101","0111001101","1101011100","0111110110",
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signal FRACTION2 : std_logic_vector(19 downto 0);
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"0110000011","1111110110","0101000110","1110011010","1110101110","0111000011",
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signal RESET_FLAGS : std_logic_vector (63 downto 0);
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"0110010110","1111001101","0011001101","1001100110","1100100101","0001100110",
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signal NEWPROB : std_logic_vector(19 downto 0);
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"1110011010","0100110011","1111001101","0111001101","0011101111","1110011010",
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signal RATIO : std_logic_vector(19 downto 0);
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"1111100011","0011001101","0101000000","1110000000","0011000000","1100000000",
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signal UPDATE_PROB : std_logic;
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"0110101011","1010101011","1110011010","0110011010","1001110010","0101010101",
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signal PROB_CHANGED : std_logic;
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"1000111001","0101010101","1100110011","0110011010","0100000000","1100000000",
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signal LOAD_DATA : std_logic;
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"1000000000");
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signal OLD_CONTEXT : std_logic_vector (5 downto 0);
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signal READ_ADDRESS : std_logic_vector (5 downto 0);
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signal DATA_FETCHED : std_logic;
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signal CONTEXT_VALID : std_logic;
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signal DATA_READY : std_logic_vector (1 downto 0);
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component DIVIDER
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port ( NUMERATOR : in std_logic_vector(9 downto 0);
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DENOMINATOR : in std_logic_vector(9 downto 0);
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RESET : in std_logic;
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CLOCK : in std_logic;
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QUOTIENT : out std_logic_vector(9 downto 0));
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end component DIVIDER;
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component UPDATER
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port ( NUMERATOR : in std_logic_vector(9 downto 0);
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DENOMINATOR : in std_logic_vector(9 downto 0);
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ENABLE : in std_logic;
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DATA_IN : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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NUMERATOR_OUT : out std_logic_vector(9 downto 0);
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DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
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UPDATE : out std_logic);
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end component UPDATER;
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component HALVING_MANAGER
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port ( TRIGGER_HALVING : in std_logic;
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INPUT_READY : in std_logic;
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NUMERATOR_IN : in std_logic_vector(9 downto 0);
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DENOMINATOR_IN : in std_logic_vector(9 downto 0);
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CONTEXT : in std_logic_vector(5 downto 0);
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RESET : in std_logic;
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CLOCK : in std_logic;
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NUMERATOR_OUT : out std_logic_vector(9 downto 0);
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DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
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OUTPUT_READY : out std_logic);
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end component HALVING_MANAGER;
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begin
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begin
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OUTPUT : process (CLOCK)
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FLAGS: process(CLOCK)
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begin
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if (CLOCK'event and CLOCK='1') then
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if (RESET='1') then
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RESET_FLAGS <= (others => '1');
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elsif LOAD_DATA = '1' then
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RESET_FLAGS(conv_integer(OLD_CONTEXT)) <= '0';
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end if;
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end if;
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end process FLAGS;
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LOAD_DATA <= UPDATE_PROB and UPDATE;
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MEMORY: process(CLOCK)
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begin
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if (CLOCK'event and CLOCK='1') then
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if SET='1' then
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READ_ADDRESS <= CONTEXT_NUMBER;
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end if;
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if (LOAD_DATA = '1') then
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PROBABILITY(conv_integer(OLD_CONTEXT)) <= NEWPROB;
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end if;
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end if;
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end process MEMORY;
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RATIO <= PROBABILITY(conv_integer(READ_ADDRESS));
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CHOOSE_FRACTION : process (READ_ADDRESS,RESET_FLAGS,RATIO)
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begin
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if (RESET_FLAGS(conv_integer(READ_ADDRESS))='1') then
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FRACTION <= HALF;
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else
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FRACTION <= RATIO;
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end if;
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end process CHOOSE_FRACTION;
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DIVISION : DIVIDER
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port map (NUMERATOR => FRACTION2(19 downto 10),
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DENOMINATOR => FRACTION2(9 downto 0),
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RESET => RESET,
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CLOCK => CLOCK,
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QUOTIENT => PROB);
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PROBUPDATE : UPDATER
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port map (NUMERATOR => FRACTION2(19 downto 10),
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DENOMINATOR => FRACTION2(9 downto 0),
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ENABLE => PROB_CHANGED,
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DATA_IN => DATA_IN,
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RESET => RESET,
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CLOCK => CLOCK,
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NUMERATOR_OUT => NEWPROB(19 downto 10),
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DENOMINATOR_OUT => NEWPROB(9 downto 0),
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UPDATE => UPDATE_PROB);
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REFRESH: HALVING_MANAGER
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port map (TRIGGER_HALVING => HALVECOUNTS,
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INPUT_READY => DATA_FETCHED,
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NUMERATOR_IN => FRACTION(19 downto 10),
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DENOMINATOR_IN => FRACTION(9 downto 0),
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CONTEXT => CONTEXT_NUMBER,
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RESET => RESET,
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CLOCK => CLOCK,
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NUMERATOR_OUT => FRACTION2(19 downto 10),
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DENOMINATOR_OUT => FRACTION2(9 downto 0),
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OUTPUT_READY => PROB_CHANGED);
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DELAY_CONTEXT : process (CLOCK)
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begin
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if CLOCK'event and CLOCK = '1' then
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OLD_CONTEXT <= CONTEXT_NUMBER;
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end if;
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end process DELAY_CONTEXT;
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IS_DATA_READY : process (CLOCK)
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begin
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begin
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if CLOCK'event and CLOCK = '1' then
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if CLOCK'event and CLOCK = '1' then
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PROB <= PROBABILITY(conv_integer(CONTEXT_NUMBER));
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if RESET='1' then
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DATA_READY <= "00";
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else
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DATA_READY <= DATA_READY(0) & PROB_CHANGED;
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end if;
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end if;
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end process OUTPUT;
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end if;
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end process IS_DATA_READY;
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CONTEXT_LOADED : process (CLOCK)
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begin
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if CLOCK'event and CLOCK='1' then
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if RESET='1' then
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CONTEXT_VALID <= '0';
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elsif SET = '1' then
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CONTEXT_VALID <= '1';
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elsif UPDATE = '1' then
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CONTEXT_VALID <= '0';
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end if;
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end if;
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end process CONTEXT_LOADED;
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DATA_FETCHED <= CONTEXT_VALID and not SET;
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READY <= (DATA_READY(1) and DATA_READY (0));-- and not SET;
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end RTL;
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end RTL;
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No newline at end of file
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No newline at end of file
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