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-- ***** BEGIN LICENSE BLOCK *****
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-- ***** BEGIN LICENSE BLOCK *****
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--
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--
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-- $Id: INPUT_CONTROL.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- $Id: INPUT_CONTROL.vhd,v 1.2 2005-05-27 16:00:28 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- *
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-- *
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- *
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-- *
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-- * The contents of this file are subject to the Mozilla Public License
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-- * The contents of this file are subject to the Mozilla Public License
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity INPUT_CONTROL is
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entity INPUT_CONTROL is
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generic(WIDTH : integer range 1 to 16 := 1);
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Port ( ENABLE : in std_logic;
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Port ( ENABLE : in std_logic;
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DATA_IN : in std_logic;
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DATA_IN : in std_logic_vector(WIDTH - 1 downto 0);
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BUFFER_CONTROL : in std_logic;
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BUFFER_CONTROL : in std_logic;
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DEMAND : in std_logic;
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DEMAND : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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SENDING : out std_logic;
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SENDING : out std_logic;
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DATA_OUT : out std_logic);
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DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0));
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end INPUT_CONTROL;
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end INPUT_CONTROL;
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architecture RTL of INPUT_CONTROL is
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architecture RTL of INPUT_CONTROL is
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component FIFO
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component FIFO
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generic( RANK : integer range 0 to 16;
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WIDTH : integer range 1 to 16);
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port( WRITE_ENABLE : in std_logic;
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port( WRITE_ENABLE : in std_logic;
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DATA_IN : in std_logic;
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DATA_IN : in std_logic_vector (WIDTH - 1 downto 0);
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READ_ENABLE : in std_logic;
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READ_ENABLE : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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DATA_OUT : out std_logic;
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DATA_OUT : out std_logic_vector (WIDTH - 1 downto 0);
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EMPTY : out std_logic);
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EMPTY : out std_logic);
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end component FIFO;
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end component FIFO;
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signal FIFO_WRITE_ENABLE : std_logic;
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signal FIFO_WRITE_ENABLE : std_logic;
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signal FIFO_READ_ENABLE : std_logic;
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signal FIFO_READ_ENABLE : std_logic;
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signal FIFO_DATA_IN : std_logic;
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signal FIFO_DATA_IN : std_logic_vector (WIDTH - 1 downto 0);
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signal FIFO_DATA_OUT : std_logic;
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signal FIFO_DATA_OUT : std_logic_vector (WIDTH - 1 downto 0);
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signal HELD : std_logic_vector (WIDTH - 1 downto 0);
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signal OUTPUT : std_logic_vector (WIDTH - 1 downto 0);
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signal TRANSMIT : std_logic;
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signal FIFO_EMPTY : std_logic;
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signal FIFO_EMPTY : std_logic;
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signal USE_BUFFER : std_logic;
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signal USE_BUFFER : std_logic;
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signal PUT_IN_BUFFER : std_logic;
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signal PUT_IN_BUFFER : std_logic;
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begin
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begin
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STORAGE : FIFO
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STORAGE : FIFO
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generic map (RANK => 8,
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WIDTH => WIDTH)
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port map(WRITE_ENABLE => FIFO_WRITE_ENABLE,
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port map(WRITE_ENABLE => FIFO_WRITE_ENABLE,
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DATA_IN => FIFO_DATA_IN,
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DATA_IN => FIFO_DATA_IN,
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READ_ENABLE => FIFO_READ_ENABLE,
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READ_ENABLE => FIFO_READ_ENABLE,
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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DATA_OUT => FIFO_DATA_OUT,
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DATA_OUT => FIFO_DATA_OUT,
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EMPTY => FIFO_EMPTY);
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EMPTY => FIFO_EMPTY);
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FIFO_WRITE_ENABLE <= ENABLE and USE_BUFFER;
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FIFO_WRITE_ENABLE <= ENABLE and USE_BUFFER;
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FIFO_DATA_IN <= DATA_IN and USE_BUFFER;
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USEFIFO: for I in 0 to WIDTH - 1 generate
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FIFO_DATA_IN(I) <= DATA_IN(I) and USE_BUFFER;
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end generate;
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FIFO_READ_ENABLE <= DEMAND and USE_BUFFER;
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FIFO_READ_ENABLE <= DEMAND and USE_BUFFER;
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PUT_IN_BUFFER <= ENABLE and BUFFER_CONTROL;
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PUT_IN_BUFFER <= ENABLE and BUFFER_CONTROL;
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USE_BUFFER <= PUT_IN_BUFFER or not FIFO_EMPTY;
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USE_BUFFER <= PUT_IN_BUFFER or not FIFO_EMPTY;
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OUTPUT_SELECT: process(USE_BUFFER,DEMAND,FIFO_DATA_OUT,ENABLE,DATA_IN)
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OUTPUT_SELECT: process(USE_BUFFER,DEMAND,FIFO_DATA_OUT,HELD,ENABLE,DATA_IN)
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begin
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begin
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if USE_BUFFER = '1' then
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if (USE_BUFFER = '1') then
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SENDING <= DEMAND;
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TRANSMIT <= DEMAND;
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DATA_OUT <= FIFO_DATA_OUT;
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if DEMAND = '1' then
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OUTPUT <= FIFO_DATA_OUT;
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else
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OUTPUT <= HELD;
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end if;
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else
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TRANSMIT <= ENABLE;
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if ENABLE = '1' then
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OUTPUT <= DATA_IN;
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else
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else
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SENDING <= ENABLE;
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OUTPUT <= HELD;
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DATA_OUT <= DATA_IN;
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end if;
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end if;
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end if;
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end process OUTPUT_SELECT;
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end process OUTPUT_SELECT;
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SENDING <= TRANSMIT;
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DATA_OUT <= OUTPUT;
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HOLD_DATA : process (CLOCK)
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begin
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if CLOCK'event and CLOCK = '1' then
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if RESET = '1' then
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HELD <= (others => '0');
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elsif TRANSMIT = '1' then
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HELD <= OUTPUT;
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end if;
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end if;
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end process HOLD_DATA;
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end RTL;
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end RTL;
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