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-- ***** BEGIN LICENSE BLOCK *****
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-- ***** BEGIN LICENSE BLOCK *****
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--
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--
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--
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-- $Id: UPDATER.vhd,v 1.2 2006-10-05 16:17:11 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- *
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--
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- The contents of this file are subject to the Mozilla Public License
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-- *
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-- Version 1.1 (the "License"); you may not use this file except in compliance
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-- * The contents of this file are subject to the Mozilla Public License
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-- with the License. You may obtain a copy of the License at
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- http://www.mozilla.org/MPL/
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-- * with the License. You may obtain a copy of the License at
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--
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-- * http://www.mozilla.org/MPL/
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-- Software distributed under the License is distributed on an "AS IS" basis,
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-- *
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-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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-- * Software distributed under the License is distributed on an "AS IS" basis,
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-- the specific language governing rights and limitations under the License.
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-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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--
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-- * the specific language governing rights and limitations under the License.
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-- The Original Code is BBC Research and Development code.
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-- *
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--
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-- * The Original Code is BBC Research and Development code.
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-- The Initial Developer of the Original Code is the British Broadcasting
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-- *
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-- Corporation.
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-- * The Initial Developer of the Original Code is the British Broadcasting
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-- Portions created by the Initial Developer are Copyright (C) 2006.
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-- * Corporation.
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-- All Rights Reserved.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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--
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-- * All Rights Reserved.
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-- Contributor(s): Peter Bleackley (Original author)
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-- *
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--
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-- * Contributor(s): Peter Bleackley (Original author)
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-- Alternatively, the contents of this file may be used under the terms of
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-- *
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-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- * Alternatively, the contents of this file may be used under the terms of
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-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- the GPL or the LGPL are applicable instead of those above. If you wish to
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-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- allow use of your version of this file only under the terms of the either
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-- * the GPL or the LGPL are applicable instead of those above. If you wish to
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-- the GPL or LGPL and not to allow others to use your version of this file
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-- * allow use of your version of this file only under the terms of the either
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-- under the MPL, indicate your decision by deleting the provisions above
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-- * the GPL or LGPL and not to allow others to use your version of this file
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-- and replace them with the notice and other provisions required by the GPL
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-- * under the MPL, indicate your decision by deleting the provisions above
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-- or LGPL. If you do not delete the provisions above, a recipient may use
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-- * and replace them with the notice and other provisions required by the GPL
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-- your version of this file under the terms of any one of the MPL, the GPL
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-- * or LGPL. If you do not delete the provisions above, a recipient may use
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-- or the LGPL.
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-- * your version of this file under the terms of any one of the MPL, the GPL
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-- * or the LGPL.
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-- * ***** END LICENSE BLOCK ***** */
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-- * ***** END LICENSE BLOCK ***** */
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity UPDATER is
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entity UPDATER is
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Port ( NUMERATOR : in std_logic_vector(9 downto 0);
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Port ( NUMERATOR : in std_logic_vector(7 downto 0);
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DENOMINATOR : in std_logic_vector(9 downto 0);
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DENOMINATOR : in std_logic_vector(7 downto 0);
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ENABLE : in std_logic;
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ENABLE : in std_logic;
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DATA_IN : in std_logic;
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DATA_IN : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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NUMERATOR_OUT : out std_logic_vector(9 downto 0);
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NUMERATOR_OUT : out std_logic_vector(7 downto 0);
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DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
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DENOMINATOR_OUT : out std_logic_vector(7 downto 0);
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UPDATE : out std_logic);
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UPDATE : out std_logic);
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end UPDATER;
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end UPDATER;
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architecture RTL of UPDATER is
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architecture RTL of UPDATER is
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signal NUMERATOR1 : std_logic_vector(9 downto 0);
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signal NUMERATOR1 : std_logic_vector(7 downto 0);
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signal NUMERATOR2 : std_logic_vector(9 downto 0);
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signal NUMERATOR2 : std_logic_vector(7 downto 0);
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signal NUMERATOR3 : std_logic_vector(9 downto 0);
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signal NUMERATOR3 : std_logic_vector(7 downto 0);
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signal NUMERATOR4 : std_logic_vector(9 downto 0);
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signal NUMERATOR4 : std_logic_vector(7 downto 0);
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signal DENOMINATOR2 : std_logic_vector(9 downto 0);
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signal DENOMINATOR2 : std_logic_vector(7 downto 0);
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signal HALVE_VALUES : std_logic;
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signal HALVE_VALUES : std_logic;
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signal HALVING_ALLOWED : std_logic;
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signal UPDATE_SWITCH : std_logic;
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signal UPDATE_SWITCH : std_logic;
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begin
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begin
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DELAY_NUMERATOR : process (CLOCK)
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DELAY_NUMERATOR : process (CLOCK)
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begin
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begin
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if CLOCK'event and CLOCK='1' then
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if CLOCK'event and CLOCK='1' then
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if RESET='1' then
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if RESET='1' then
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NUMERATOR1<="0000000001";
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NUMERATOR1<="00000001";
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else
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else
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NUMERATOR1<=NUMERATOR;
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NUMERATOR1<=NUMERATOR;
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end if;
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end if;
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end if;
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end if;
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end process DELAY_NUMERATOR;
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end process DELAY_NUMERATOR;
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INCREMENT_NUMERATOR : process (CLOCK)
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INCREMENT_NUMERATOR : process (CLOCK)
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begin
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begin
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if CLOCK'event and CLOCK = '1' then
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if CLOCK'event and CLOCK = '1' then
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if RESET = '1' then
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if RESET = '1' then
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NUMERATOR2 <= "0000000001";
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NUMERATOR2 <= "00000001";
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else
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else
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NUMERATOR2 <= NUMERATOR + "0000000001";
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NUMERATOR2 <= NUMERATOR + "00000001";
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end if;
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end if;
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end if;
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end if;
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end process INCREMENT_NUMERATOR;
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end process INCREMENT_NUMERATOR;
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HALVE_NUMERATOR : process (CLOCK)
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HALVE_NUMERATOR : process (CLOCK)
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begin
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begin
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if CLOCK'event and CLOCK='1' then
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if CLOCK'event and CLOCK='1' then
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if RESET='1' then
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if RESET='1' then
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NUMERATOR3 <= "0000000001";
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NUMERATOR3 <= "00000001";
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else
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else
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NUMERATOR3 <= ('0' & NUMERATOR(9 downto 1)) + "0000000001";
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NUMERATOR3 <= ('0' & NUMERATOR(7 downto 1)) + "00000001";
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end if;
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end if;
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end if;
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end if;
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end process HALVE_NUMERATOR;
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end process HALVE_NUMERATOR;
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INCREMENT_AND_HALVE_NUMERATOR : process (CLOCK)
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INCREMENT_AND_HALVE_NUMERATOR : process (CLOCK)
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begin
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begin
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if CLOCK'event and CLOCK='1' then
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if CLOCK'event and CLOCK='1' then
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if RESET='1' then
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if RESET='1' then
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NUMERATOR4 <= "0000000001";
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NUMERATOR4 <= "00000001";
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else
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else
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NUMERATOR4 <= ('0' & NUMERATOR(9 downto 1)) + "0000000001" + ("000000000" & NUMERATOR(0));
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NUMERATOR4 <= ('0' & NUMERATOR(7 downto 1)) + "00000001" + ("0000000" & NUMERATOR(0));
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end if;
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end if;
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end if;
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end if;
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end process INCREMENT_AND_HALVE_NUMERATOR;
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end process INCREMENT_AND_HALVE_NUMERATOR;
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INCREMENT_DENOMINATOR : process (CLOCK)
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INCREMENT_DENOMINATOR : process (CLOCK)
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begin
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begin
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if CLOCK'event and CLOCK='1' then
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if CLOCK'event and CLOCK='1' then
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if RESET='1' then
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if RESET='1' then
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DENOMINATOR2 <= "0000000010";
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DENOMINATOR2 <= "00000010";
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else
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else
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DENOMINATOR2 <= DENOMINATOR + "0000000001";
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DENOMINATOR2 <= DENOMINATOR + "00000001";
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end if;
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end if;
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end if;
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end if;
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end process INCREMENT_DENOMINATOR;
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end process INCREMENT_DENOMINATOR;
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HALVE_DENOMINATOR : process (DENOMINATOR)
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HALVE_DENOMINATOR : process (DENOMINATOR)
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begin
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begin
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if (DENOMINATOR = "1111111111") then
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if (DENOMINATOR = "11111111") then
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HALVE_VALUES <= '1';
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HALVE_VALUES <= '1';
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else
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else
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HALVE_VALUES <= '0';
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HALVE_VALUES <= '0';
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end if;
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end if;
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end process HALVE_DENOMINATOR;
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end process HALVE_DENOMINATOR;
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end if;
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end if;
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end process OUTPUT_NUMERATOR;
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end process OUTPUT_NUMERATOR;
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UPDATE_SWITCH <= DATA_IN xor NUMERATOR(0);
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UPDATE_SWITCH <= DATA_IN xor NUMERATOR(0);
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OUTPUT_DENOMINATOR : process(HALVING_ALLOWED,DENOMINATOR,DENOMINATOR2,UPDATE_SWITCH,HALVE_VALUES,NUMERATOR)
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OUTPUT_DENOMINATOR : process(DENOMINATOR,DENOMINATOR2,UPDATE_SWITCH,HALVE_VALUES)
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begin
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begin
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if HALVE_VALUES='1' then
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if HALVE_VALUES='1' then
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if UPDATE_SWITCH = '1' then
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if UPDATE_SWITCH = '1' then
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DENOMINATOR_OUT <= "1000000010";
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DENOMINATOR_OUT <= "10000010";
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else
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else
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DENOMINATOR_OUT <= "1000000001";
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DENOMINATOR_OUT <= "10000001";
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end if;
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end if;
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else
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else
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DENOMINATOR_OUT<=DENOMINATOR2;
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DENOMINATOR_OUT<=DENOMINATOR2;
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end if;
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end if;
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end process OUTPUT_DENOMINATOR;
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end process OUTPUT_DENOMINATOR;
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