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-- ***** BEGIN LICENSE BLOCK *****
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-- ***** BEGIN LICENSE BLOCK *****
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--
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--
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-- $Id: STORAGE_REGISTER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- $Id: STORAGE_REGISTER.vhd,v 1.2 2005-05-27 16:00:29 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- *
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-- *
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- *
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-- *
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-- * The contents of this file are subject to the Mozilla Public License
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-- * The contents of this file are subject to the Mozilla Public License
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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OUTPUT : out std_logic_vector(15 downto 0));
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OUTPUT : out std_logic_vector(15 downto 0));
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end entity STORAGE_REGISTER;
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end entity STORAGE_REGISTER;
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architecture RTL of STORAGE_REGISTER is
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architecture RTL of STORAGE_REGISTER is
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component STORE_BLOCK
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port(LOAD_IN, SHIFT_IN, SHIFT, ENABLE, CLK: in std_logic;
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OUTPUT: out std_logic);
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end component STORE_BLOCK;
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signal SHIFT_LSBS: std_logic;
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signal SHIFT_LSBS: std_logic;
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signal SET_RESET: std_logic;
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signal SET_RESET: std_logic;
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signal ENABLE_MSB: std_logic;
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signal ENABLE_MSB: std_logic;
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signal ENABLE_LSBS: std_logic;
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signal ENABLE_LSBS: std_logic;
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signal D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15: std_logic;
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signal D: std_logic_vector(15 downto 0);
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signal Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15: std_logic;
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signal Q: std_logic_vector(15 downto 0);
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begin
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begin
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-- control logic
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-- control logic
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SET_RESET <= SET_VALUE or RESET;
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SET_RESET <= SET_VALUE or RESET;
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ENABLE_MSB <= SET_RESET or SHIFT_ALL;
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ENABLE_MSB <= SET_RESET or SHIFT_ALL;
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SHIFT_LSBS <= SHIFT_ALL or SHIFT_MOST;
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SHIFT_LSBS <= SHIFT_ALL or SHIFT_MOST;
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ENABLE_LSBS <= SET_RESET or SHIFT_LSBS;
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ENABLE_LSBS <= SET_RESET or SHIFT_LSBS;
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-- outputs
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-- outputs
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OUTPUT(0) <= Q0;
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OUTPUT <= Q;
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OUTPUT(1) <= Q1;
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OUTPUT(2) <= Q2;
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OUTPUT(3) <= Q3;
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OUTPUT(4) <= Q4;
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OUTPUT(5) <= Q5;
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OUTPUT(6) <= Q6;
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OUTPUT(7) <= Q7;
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OUTPUT(8) <= Q8;
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OUTPUT(9) <= Q9;
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OUTPUT(10) <= Q10;
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OUTPUT(11) <= Q11;
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OUTPUT(12) <= Q12;
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OUTPUT(13) <= Q13;
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OUTPUT(14) <= Q14;
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OUTPUT(15) <= Q15;
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-- initialisation
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-- initialisation
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INIT: process(RESET,LOAD)
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INIT: process(RESET,LOAD)
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begin
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begin
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if RESET = '1' then
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if RESET = '1' then
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D0 <= '0';
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D <= "0000000000000000";
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D1 <= '0';
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D2 <= '0';
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D3 <= '0';
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D4 <= '0';
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D5 <= '0';
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D6 <= '0';
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D7 <= '0';
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D8 <= '0';
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D9 <= '0';
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D10 <= '0';
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D11 <= '0';
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D12 <= '0';
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D13 <= '0';
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D14 <= '0';
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D15 <= '0';
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else
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else
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D0 <= LOAD(0);
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D <= LOAD;
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D1 <= LOAD(1);
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D2 <= LOAD(2);
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D3 <= LOAD(3);
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D4 <= LOAD(4);
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D5 <= LOAD(5);
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D6 <= LOAD(6);
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D7 <= LOAD(7);
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D8 <= LOAD(8);
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D9 <= LOAD(9);
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D10 <= LOAD(10);
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D11 <= LOAD(11);
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D12 <= LOAD(12);
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D13 <= LOAD(13);
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D14 <= LOAD(14);
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D15 <= LOAD(15);
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end if;
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end if;
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end process INIT;
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end process INIT;
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-- storage
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-- storage
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STORE0: STORE_BLOCK
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STORE: process (CLOCK)
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port map(LOAD_IN => D0,
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begin
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SHIFT_IN => SHIFT_IN,
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if CLOCK'event and CLOCK = '1' then
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SHIFT => SHIFT_LSBS,
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if ENABLE_LSBS = '1' then
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ENABLE => ENABLE_LSBS,
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if SHIFT_LSBS = '1' then
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CLK => CLOCK,
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Q(14 downto 0) <= Q(13 downto 0) & SHIFT_IN;
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OUTPUT => Q0);
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else
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Q(14 downto 0) <= D(14 downto 0);
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STORE1: STORE_BLOCK
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end if;
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port map(LOAD_IN => D1,
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end if;
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SHIFT_IN => Q0,
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if ENABLE_MSB = '1' then
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SHIFT => SHIFT_LSBS,
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if SHIFT_ALL = '1' then
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ENABLE => ENABLE_LSBS,
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Q(15) <= Q(14);
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CLK => CLOCK,
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else
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OUTPUT => Q1);
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Q(15) <= D(15);
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end if;
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STORE2: STORE_BLOCK
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end if;
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port map(LOAD_IN => D2,
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end if;
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SHIFT_IN => Q1,
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end process STORE;
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q2);
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STORE3: STORE_BLOCK
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port map(LOAD_IN => D3,
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SHIFT_IN => Q2,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q3);
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STORE4: STORE_BLOCK
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port map(LOAD_IN => D4,
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SHIFT_IN => Q3,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q4);
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STORE5: STORE_BLOCK
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port map(LOAD_IN => D5,
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SHIFT_IN => Q4,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q5);
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STORE6: STORE_BLOCK
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port map(LOAD_IN => D6,
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SHIFT_IN => Q5,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q6);
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STORE7: STORE_BLOCK
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port map(LOAD_IN => D7,
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SHIFT_IN => Q6,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q7);
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STORE8: STORE_BLOCK
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port map(LOAD_IN => D8,
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SHIFT_IN => Q7,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q8);
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STORE9: STORE_BLOCK
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port map(LOAD_IN => D9,
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SHIFT_IN => Q8,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q9);
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STORE10: STORE_BLOCK
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port map(LOAD_IN => D10,
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SHIFT_IN => Q9,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q10);
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STORE11: STORE_BLOCK
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port map(LOAD_IN => D11,
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SHIFT_IN => Q10,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q11);
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STORE12: STORE_BLOCK
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port map(LOAD_IN => D12,
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SHIFT_IN => Q11,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q12);
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STORE13: STORE_BLOCK
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port map(LOAD_IN => D13,
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SHIFT_IN => Q12,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q13);
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STORE14: STORE_BLOCK
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port map(LOAD_IN => D14,
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SHIFT_IN => Q13,
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SHIFT => SHIFT_LSBS,
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ENABLE => ENABLE_LSBS,
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CLK => CLOCK,
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OUTPUT => Q14);
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STORE15: STORE_BLOCK
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port map(LOAD_IN => D15,
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SHIFT_IN => Q14,
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SHIFT => SHIFT_ALL,
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ENABLE => ENABLE_MSB,
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CLK => CLOCK,
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OUTPUT => Q15);
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end architecture RTL;
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end architecture RTL;
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No newline at end of file
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No newline at end of file
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