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-- ***** BEGIN LICENSE BLOCK *****
-- ***** BEGIN LICENSE BLOCK *****
-- 
-- 
-- $Id: STORAGE_REGISTER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
-- $Id: STORAGE_REGISTER.vhd,v 1.2 2005-05-27 16:00:29 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
-- *
-- * The contents of this file are subject to the Mozilla Public License
-- * The contents of this file are subject to the Mozilla Public License
-- * Version 1.1 (the "License"); you may not use this file except in compliance
-- * Version 1.1 (the "License"); you may not use this file except in compliance
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           CLOCK : in std_logic;
           CLOCK : in std_logic;
           OUTPUT : out std_logic_vector(15 downto 0));
           OUTPUT : out std_logic_vector(15 downto 0));
end entity STORAGE_REGISTER;
end entity STORAGE_REGISTER;
 
 
architecture RTL of STORAGE_REGISTER is
architecture RTL of STORAGE_REGISTER is
        component STORE_BLOCK
 
        port(LOAD_IN, SHIFT_IN, SHIFT, ENABLE, CLK:     in std_logic;
 
        OUTPUT: out std_logic);
 
        end component STORE_BLOCK;
 
        signal SHIFT_LSBS: std_logic;
        signal SHIFT_LSBS: std_logic;
        signal SET_RESET: std_logic;
        signal SET_RESET: std_logic;
        signal ENABLE_MSB: std_logic;
        signal ENABLE_MSB: std_logic;
        signal ENABLE_LSBS: std_logic;
        signal ENABLE_LSBS: std_logic;
        signal D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15:   std_logic;
        signal D:       std_logic_vector(15 downto 0);
        signal Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15:   std_logic;
        signal Q:       std_logic_vector(15 downto 0);
begin
begin
 
 
-- control logic
-- control logic
        SET_RESET <= SET_VALUE or RESET;
        SET_RESET <= SET_VALUE or RESET;
        ENABLE_MSB <= SET_RESET or SHIFT_ALL;
        ENABLE_MSB <= SET_RESET or SHIFT_ALL;
        SHIFT_LSBS <= SHIFT_ALL or SHIFT_MOST;
        SHIFT_LSBS <= SHIFT_ALL or SHIFT_MOST;
        ENABLE_LSBS <= SET_RESET or SHIFT_LSBS;
        ENABLE_LSBS <= SET_RESET or SHIFT_LSBS;
 
 
-- outputs
-- outputs
 
 
        OUTPUT(0) <= Q0;
        OUTPUT <= Q;
        OUTPUT(1) <= Q1;
 
        OUTPUT(2) <= Q2;
 
        OUTPUT(3) <= Q3;
 
        OUTPUT(4) <= Q4;
 
        OUTPUT(5) <= Q5;
 
        OUTPUT(6) <= Q6;
 
        OUTPUT(7) <= Q7;
 
        OUTPUT(8) <= Q8;
 
        OUTPUT(9) <= Q9;
 
        OUTPUT(10) <= Q10;
 
        OUTPUT(11) <= Q11;
 
        OUTPUT(12) <= Q12;
 
        OUTPUT(13) <= Q13;
 
        OUTPUT(14) <= Q14;
 
        OUTPUT(15) <= Q15;
 
 
 
-- initialisation
-- initialisation
 
 
INIT:   process(RESET,LOAD)
INIT:   process(RESET,LOAD)
begin
begin
        if RESET = '1' then
        if RESET = '1' then
        D0 <= '0';
                D <= "0000000000000000";
        D1 <= '0';
 
        D2 <= '0';
 
        D3 <= '0';
 
        D4 <= '0';
 
        D5 <= '0';
 
        D6 <= '0';
 
        D7 <= '0';
 
        D8 <= '0';
 
        D9 <= '0';
 
        D10 <= '0';
 
        D11 <= '0';
 
        D12 <= '0';
 
        D13 <= '0';
 
        D14 <= '0';
 
        D15 <= '0';
 
        else
        else
        D0 <= LOAD(0);
                D <= LOAD;
        D1 <= LOAD(1);
 
        D2 <= LOAD(2);
 
        D3 <= LOAD(3);
 
        D4 <= LOAD(4);
 
        D5 <= LOAD(5);
 
        D6 <= LOAD(6);
 
        D7 <= LOAD(7);
 
        D8 <= LOAD(8);
 
        D9 <= LOAD(9);
 
        D10 <= LOAD(10);
 
        D11 <= LOAD(11);
 
        D12 <= LOAD(12);
 
        D13 <= LOAD(13);
 
        D14 <= LOAD(14);
 
        D15 <= LOAD(15);
 
        end if;
        end if;
end process INIT;
end process INIT;
 
 
-- storage
-- storage
 
 
        STORE0: STORE_BLOCK
        STORE: process (CLOCK)
        port map(LOAD_IN => D0,
        begin
                                SHIFT_IN => SHIFT_IN,
                if CLOCK'event and CLOCK = '1' then
                                SHIFT => SHIFT_LSBS,
                        if      ENABLE_LSBS = '1' then
                                ENABLE => ENABLE_LSBS,
                                if      SHIFT_LSBS = '1' then
                                CLK => CLOCK,
                                        Q(14 downto 0) <= Q(13 downto 0) & SHIFT_IN;
                                OUTPUT => Q0);
                                else
 
                                        Q(14 downto 0) <= D(14 downto 0);
        STORE1: STORE_BLOCK
                                end if;
        port map(LOAD_IN => D1,
                        end if;
                                SHIFT_IN => Q0,
                        if ENABLE_MSB = '1' then
                                SHIFT => SHIFT_LSBS,
                                if SHIFT_ALL = '1' then
                                ENABLE => ENABLE_LSBS,
                                        Q(15) <= Q(14);
                                CLK => CLOCK,
                                else
                                OUTPUT => Q1);
                                        Q(15) <= D(15);
 
                                end if;
        STORE2: STORE_BLOCK
                        end if;
        port map(LOAD_IN => D2,
                end if;
                                SHIFT_IN => Q1,
        end process STORE;
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q2);
 
 
 
        STORE3: STORE_BLOCK
 
        port map(LOAD_IN => D3,
 
                                SHIFT_IN => Q2,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q3);
 
 
 
        STORE4: STORE_BLOCK
 
        port map(LOAD_IN => D4,
 
                                SHIFT_IN => Q3,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q4);
 
 
 
        STORE5: STORE_BLOCK
 
        port map(LOAD_IN => D5,
 
                                SHIFT_IN => Q4,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q5);
 
 
 
        STORE6: STORE_BLOCK
 
        port map(LOAD_IN => D6,
 
                                SHIFT_IN => Q5,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q6);
 
 
 
        STORE7: STORE_BLOCK
 
        port map(LOAD_IN => D7,
 
                                SHIFT_IN => Q6,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q7);
 
 
 
        STORE8: STORE_BLOCK
 
        port map(LOAD_IN => D8,
 
                                SHIFT_IN => Q7,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q8);
 
 
 
        STORE9: STORE_BLOCK
 
        port map(LOAD_IN => D9,
 
                                SHIFT_IN => Q8,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q9);
 
 
 
        STORE10: STORE_BLOCK
 
        port map(LOAD_IN => D10,
 
                                SHIFT_IN => Q9,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q10);
 
 
 
        STORE11: STORE_BLOCK
 
        port map(LOAD_IN => D11,
 
                                SHIFT_IN => Q10,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q11);
 
 
 
        STORE12: STORE_BLOCK
 
        port map(LOAD_IN => D12,
 
                                SHIFT_IN => Q11,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q12);
 
 
 
        STORE13: STORE_BLOCK
 
        port map(LOAD_IN => D13,
 
                                SHIFT_IN => Q12,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q13);
 
 
 
        STORE14: STORE_BLOCK
 
        port map(LOAD_IN => D14,
 
                                SHIFT_IN => Q13,
 
                                SHIFT => SHIFT_LSBS,
 
                                ENABLE => ENABLE_LSBS,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q14);
 
 
 
        STORE15: STORE_BLOCK
 
        port map(LOAD_IN => D15,
 
                                SHIFT_IN => Q14,
 
                                SHIFT => SHIFT_ALL,
 
                                ENABLE => ENABLE_MSB,
 
                                CLK => CLOCK,
 
                                OUTPUT => Q15);
 
 
 
 
 
 
 
end architecture RTL;
end architecture RTL;
 
 
 
 
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