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-- ***** BEGIN LICENSE BLOCK *****
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-- ***** BEGIN LICENSE BLOCK *****
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--
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--
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--
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-- $Id: ARITHMETICCODER.vhd,v 1.4 2006-10-05 16:17:13 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- *
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--
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- The contents of this file are subject to the Mozilla Public License
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-- *
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-- Version 1.1 (the "License"); you may not use this file except in compliance
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-- * The contents of this file are subject to the Mozilla Public License
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-- with the License. You may obtain a copy of the License at
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- http://www.mozilla.org/MPL/
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-- * with the License. You may obtain a copy of the License at
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--
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-- * http://www.mozilla.org/MPL/
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-- Software distributed under the License is distributed on an "AS IS" basis,
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-- *
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-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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-- * Software distributed under the License is distributed on an "AS IS" basis,
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-- the specific language governing rights and limitations under the License.
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-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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--
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-- * the specific language governing rights and limitations under the License.
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-- The Original Code is BBC Research and Development code.
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-- *
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--
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-- * The Original Code is BBC Research and Development code.
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-- The Initial Developer of the Original Code is the British Broadcasting
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-- *
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-- Corporation.
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-- * The Initial Developer of the Original Code is the British Broadcasting
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-- Portions created by the Initial Developer are Copyright (C) 2006.
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-- * Corporation.
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-- All Rights Reserved.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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--
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-- * All Rights Reserved.
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-- Contributor(s): Peter Bleackley (Original author)
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-- *
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--
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-- * Contributor(s): Peter Bleackley (Original author)
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-- Alternatively, the contents of this file may be used under the terms of
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-- *
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-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- * Alternatively, the contents of this file may be used under the terms of
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-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- the GPL or the LGPL are applicable instead of those above. If you wish to
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-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- allow use of your version of this file only under the terms of the either
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-- * the GPL or the LGPL are applicable instead of those above. If you wish to
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-- the GPL or LGPL and not to allow others to use your version of this file
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-- * allow use of your version of this file only under the terms of the either
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-- under the MPL, indicate your decision by deleting the provisions above
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-- * the GPL or LGPL and not to allow others to use your version of this file
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-- and replace them with the notice and other provisions required by the GPL
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-- * under the MPL, indicate your decision by deleting the provisions above
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-- or LGPL. If you do not delete the provisions above, a recipient may use
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-- * and replace them with the notice and other provisions required by the GPL
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-- your version of this file under the terms of any one of the MPL, the GPL
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-- * or LGPL. If you do not delete the provisions above, a recipient may use
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-- or the LGPL.
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-- * your version of this file under the terms of any one of the MPL, the GPL
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-- * or the LGPL.
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-- * ***** END LICENSE BLOCK ***** */
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-- * ***** END LICENSE BLOCK ***** */
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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TRIGGER_OUTPUT : out std_logic;
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TRIGGER_OUTPUT : out std_logic;
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TRIGGER_FOLLOW : out std_logic);
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TRIGGER_FOLLOW : out std_logic);
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end component CONVERGENCE_CHECK;
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end component CONVERGENCE_CHECK;
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component ARITHMETIC_UNIT
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component ARITHMETIC_UNIT
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port ( DIFFERENCE : in std_logic_vector(15 downto 0);
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port ( DIFFERENCE : in std_logic_vector(15 downto 0);
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PROB : in std_logic_vector(9 downto 0);
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PROB : in std_logic_vector(7 downto 0);
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LOW : in std_logic_vector(15 downto 0);
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LOW : in std_logic_vector(15 downto 0);
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ENABLE : in std_logic;
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ENABLE : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
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DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
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UPDATE : in std_logic;
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UPDATE : in std_logic;
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DATA_IN : in std_logic;
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DATA_IN : in std_logic;
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HALVECOUNTS : in std_logic;
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HALVECOUNTS : in std_logic;
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RESET : in std_logic;
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RESET : in std_logic;
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CLOCK : in std_logic;
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CLOCK : in std_logic;
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PROB : out std_logic_vector(9 downto 0);
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PROB : out std_logic_vector(7 downto 0);
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READY : out std_logic);
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READY : out std_logic);
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end component CONTEXT_MANAGER;
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end component CONTEXT_MANAGER;
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signal HIGH_SET : std_logic;
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signal HIGH_SET : std_logic;
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signal LOW_SET : std_logic;
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signal LOW_SET : std_logic;
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signal TRIGGER_SHIFT : std_logic;
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signal TRIGGER_SHIFT : std_logic;
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signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0);
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signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0);
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signal DIFFERENCE_OUT : std_logic_vector (15 downto 0);
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signal DIFFERENCE_OUT : std_logic_vector (15 downto 0);
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signal HIGH_OUT : std_logic_vector (15 downto 0);
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signal HIGH_OUT : std_logic_vector (15 downto 0);
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signal LOW_OUT : std_logic_vector (15 downto 0);
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signal LOW_OUT : std_logic_vector (15 downto 0);
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signal PROB : std_logic_vector (9 downto 0);
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signal PROB : std_logic_vector (7 downto 0);
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signal CONTEXT_SELECT : std_logic_vector (5 downto 0);
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signal CONTEXT_SELECT : std_logic_vector (5 downto 0);
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signal PROB_AVAILABLE : std_logic;
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signal PROB_AVAILABLE : std_logic;
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signal BUFFERCONTEXT : std_logic;
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signal BUFFERCONTEXT : std_logic;
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signal DATA_IN2 : std_logic_vector(0 downto 0);
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signal DATA_IN2 : std_logic_vector(0 downto 0);
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signal BUFFERED_DATA2 : std_logic_vector(0 downto 0);
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signal BUFFERED_DATA2 : std_logic_vector(0 downto 0);
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