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-- ***** BEGIN LICENSE BLOCK *****
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--
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-- $Id: OUTPUT_UNIT.vhd,v 1.2 2005-05-27 16:00:30 petebleackley Exp $ $Name: not supported by cvs2svn $
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-- *
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-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
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-- *
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-- * The contents of this file are subject to the Mozilla Public License
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-- * Version 1.1 (the "License"); you may not use this file except in compliance
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-- * with the License. You may obtain a copy of the License at
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-- * http://www.mozilla.org/MPL/
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-- *
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-- * Software distributed under the License is distributed on an "AS IS" basis,
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-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
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-- * the specific language governing rights and limitations under the License.
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-- *
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-- * The Original Code is BBC Research and Development code.
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-- *
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-- * The Initial Developer of the Original Code is the British Broadcasting
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-- * Corporation.
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-- * Portions created by the Initial Developer are Copyright (C) 2004.
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-- * All Rights Reserved.
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-- *
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-- * Contributor(s): Peter Bleackley (Original author)
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-- *
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-- * Alternatively, the contents of this file may be used under the terms of
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-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
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-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
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-- * the GPL or the LGPL are applicable instead of those above. If you wish to
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-- * allow use of your version of this file only under the terms of the either
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-- * the GPL or LGPL and not to allow others to use your version of this file
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-- * under the MPL, indicate your decision by deleting the provisions above
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-- * and replace them with the notice and other provisions required by the GPL
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-- * or LGPL. If you do not delete the provisions above, a recipient may use
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-- * your version of this file under the terms of any one of the MPL, the GPL
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-- * or the LGPL.
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-- * ***** END LICENSE BLOCK ***** */
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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FOLLOW_COUNTER_TEST : out std_logic;
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FOLLOW_COUNTER_TEST : out std_logic;
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SHIFT : out std_logic);
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SHIFT : out std_logic);
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end OUTPUT_UNIT;
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end OUTPUT_UNIT;
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architecture RTL of OUTPUT_UNIT is
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architecture RTL of OUTPUT_UNIT is
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component D_TYPE
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port(D,CLOCK: in std_logic;
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Q: out std_logic);
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end component D_TYPE;
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signal OUTVALUE: std_logic;
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signal OUTVALUE: std_logic;
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signal DELAYED: std_logic;
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signal DELAYED: std_logic;
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signal NOFOLLOW: std_logic;
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signal NOFOLLOW: std_logic;
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signal ACTIVE: std_logic;
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signal ACTIVE: std_logic;
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signal FEEDBACK : std_logic;
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signal FEEDBACK : std_logic;
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SHIFT <= FEEDBACK;
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SHIFT <= FEEDBACK;
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SENDING <= ACTIVE;
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SENDING <= ACTIVE;
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-- sequential logic
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-- sequential logic
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FLIP_FLOP: D_TYPE
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FLIP_FLOP: process (CLOCK)
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port map(D => ACTIVE,
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begin
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CLOCK => CLOCK,
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if CLOCK'event and CLOCK = '1' then
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Q => DELAYED);
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DELAYED <= ACTIVE;
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end if;
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end process FLIP_FLOP;
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end RTL;
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end RTL;
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