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[/] [dirac/] [trunk/] [src/] [testbench/] [ArithmeticCoderTestbench.vhd] - Diff between revs 2 and 4
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| Rev 2 |
Rev 4 |
| Line 25... |
Line 25... |
generic(
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generic(
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PROB : std_logic_vector (9 downto 0));
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PROB : std_logic_vector (9 downto 0));
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PORT(
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PORT(
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ENABLE : IN std_logic;
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ENABLE : IN std_logic;
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DATA_IN : IN std_logic;
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DATA_IN : IN std_logic;
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CONTEXT_ENABLE : in std_logic;
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CONTEXT_IN : in std_logic_vector (5 downto 0);
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RESET : IN std_logic;
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RESET : IN std_logic;
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CLOCK : IN std_logic;
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CLOCK : IN std_logic;
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SENDING : OUT std_logic;
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SENDING : OUT std_logic;
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DATA_OUT : OUT std_logic
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DATA_OUT : OUT std_logic
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);
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);
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| Line 53... |
Line 51... |
SIGNAL SENDING : std_logic;
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SIGNAL SENDING : std_logic;
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SIGNAL DATA_OUT : std_logic;
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SIGNAL DATA_OUT : std_logic;
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signal TRANSMIT : std_logic;
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signal TRANSMIT : std_logic;
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signal DATA_TRANSFER : std_logic;
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signal DATA_TRANSFER : std_logic;
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constant PERIOD : time := 10 ns;
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constant PERIOD : time := 10 ns;
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signal CONTEXT_ENABLE : std_logic;
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file TESTDATA : text is in "raw_data";
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signal CONTEXT : std_logic_vector (5 downto 0) := "000000";
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file TESTDATA : text is in "";
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file RESULTS : text is out "results";
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file RESULTS : text is out "results";
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BEGIN
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BEGIN
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uut: arithmeticcoder
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uut: arithmeticcoder
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generic map(
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generic map(
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PROB => "1110010000")
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PROB => "1110010000")
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PORT MAP(
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PORT MAP(
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ENABLE => ENABLE,
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ENABLE => ENABLE,
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DATA_IN => DATA_IN,
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DATA_IN => DATA_IN,
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CONTEXT_ENABLE => CONTEXT_ENABLE,
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CONTEXT_IN => CONTEXT,
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RESET => RESET,
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RESET => RESET,
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CLOCK => CLOCK,
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CLOCK => CLOCK,
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SENDING => TRANSMIT,
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SENDING => TRANSMIT,
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DATA_OUT => DATA_TRANSFER
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DATA_OUT => DATA_TRANSFER
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);
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);
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| Line 133... |
Line 127... |
else
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else
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write(OUTLINE,DATA_OUT);
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write(OUTLINE,DATA_OUT);
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if (WRITTEN mod 32) = 31 then
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if (WRITTEN mod 32) = 31 then
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writeline(RESULTS,OUTLINE);
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writeline(RESULTS,OUTLINE);
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end if;
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end if;
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end if;
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end loop;
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end loop;
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end process;
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end process;
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-- *** End Test Bench - User Defined Section ***
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-- *** End Test Bench - User Defined Section ***
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