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https://opencores.org/ocsvn/distributed_intelligence/distributed_intelligence/trunk
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity bus_access_x16 is
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entity bus_access_x16 is
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Port ( clk : in STD_LOGIC;
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Port ( en : in STD_LOGIC;
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en : in STD_LOGIC;
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dataRead : in STD_LOGIC_VECTOR (15 downto 0);
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dataRead : in STD_LOGIC_VECTOR (15 downto 0);
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dataWrite : out STD_LOGIC_VECTOR (15 downto 0));
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dataWrite : out STD_LOGIC_VECTOR (15 downto 0));
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end bus_access_x16;
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end bus_access_x16;
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architecture Behavioral of bus_access_x16 is
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architecture Behavioral of bus_access_x16 is
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begin
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begin
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process(clk, en, dataRead)
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process(en, dataRead)
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begin
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begin
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if clk'event and clk = '1' then
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if en = '1' then
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if en = '1' then
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dataWrite <= dataRead;
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dataWrite <= dataRead;
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else
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else
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dataWrite <= (others => 'Z');
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dataWrite <= (others => 'Z');
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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