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https://opencores.org/ocsvn/distributed_intelligence/distributed_intelligence/trunk
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dataOut : out STD_LOGIC_VECTOR (15 downto 0));
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dataOut : out STD_LOGIC_VECTOR (15 downto 0));
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end bus_register_x16;
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end bus_register_x16;
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architecture Behavioral of bus_register_x16 is
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architecture Behavioral of bus_register_x16 is
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signal data: std_logic_vector(15 downto 0);
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signal data: std_logic_vector(15 downto 0);
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component bus_access_x16
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Port ( en : in STD_LOGIC;
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dataRead : in STD_LOGIC_VECTOR (15 downto 0);
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dataWrite : out STD_LOGIC_VECTOR (15 downto 0));
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end component;
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begin
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begin
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ba: bus_access_x16
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tristate: process(we, data) is
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port map( en => we,
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begin
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dataRead=>data,
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if we = '1' then
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dataWrite=>dataOut);
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dataOut <= data;
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else
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dataOut <= (others=>'Z');
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end if;
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end process;
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readData: process(clk) is
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readData: process(clk) is
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if re = '1' then
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if re = '1' then
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