| Line 42... |
Line 42... |
prev_uP : in STD_LOGIC_VECTOR (7 downto 0);
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prev_uP : in STD_LOGIC_VECTOR (7 downto 0);
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next_uP : out STD_LOGIC_VECTOR (7 downto 0));
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next_uP : out STD_LOGIC_VECTOR (7 downto 0));
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end mini_uP_x16;
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end mini_uP_x16;
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architecture Behavioral of mini_uP_x16 is
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architecture Behavioral of mini_uP_x16 is
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-- Data bus
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signal dataBus1, dataBus2: std_logic_vector(15 downto 0); -- For ALU data1 and data2
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signal dataBus1, dataBus2: std_logic_vector(15 downto 0); -- For ALU data1 and data2
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signal accumulator: std_logic_vector(15 downto 0);
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signal mainDataBus: std_logic_vector(15 downto 0);
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signal mainDataBus: std_logic_vector(15 downto 0);
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-- ALU signals (driven by both the ALU and the identifier)
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signal accumulator: std_logic_vector(15 downto 0);
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signal ALUoverflow: std_logic;
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signal opCode: ALU_OPCODE;
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signal opCode: ALU_OPCODE;
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-- Control signals (driven by the controler)
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signal register_control: std_logic_vector(7 downto 0); -- re1 we1 re2 we2 re3 we3 re4 we4
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signal register_control: std_logic_vector(7 downto 0); -- re1 we1 re2 we2 re3 we3 re4 we4
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signal stack_control : std_logic_vector(1 downto 0); -- en push/pop
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signal stack_control : std_logic_vector(1 downto 0); -- en push/pop
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signal PC_control : std_logic;
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signal PC_control : std_logic;
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signal inc_PC: std_logic;
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signal inc_PC: std_logic;
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-- Id signal (driven by the identifier)
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signal uP_id: std_logic_vector(7 downto 0);
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signal uP_id: std_logic_vector(7 downto 0);
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-- Watchdog (driven by both the watchdog and the controler)
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signal watchdog_left: std_logic_vector(15 downto 0);
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signal watchdog_left: std_logic_vector(15 downto 0);
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signal watchdog_rst_value: std_logic_vector(15 downto 0);
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signal watchdog_rst_value: std_logic_vector(15 downto 0);
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signal watchdog_rst: std_logic;
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signal watchdog_rst: std_logic;
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signal watchdog_control : std_logic_vector(1 downto 0);
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signal watchdog_control : std_logic_vector(1 downto 0);
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| Line 127... |
Line 133... |
dataA : out STD_LOGIC_VECTOR (15 downto 0);
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dataA : out STD_LOGIC_VECTOR (15 downto 0);
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op : in ALU_OPCODE;
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op : in ALU_OPCODE;
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overflow: out STD_LOGIC );
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overflow: out STD_LOGIC );
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end component;
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end component;
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begin
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begin
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-- The program counter
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program_counter: binary_counter_x16
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program_counter: binary_counter_x16
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port map( clk => clk,
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port map( clk => clk,
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set => PC_control,
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set => PC_control,
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inc => inc_PC,
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inc => inc_PC,
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set_value => mainDataBus,
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set_value => mainDataBus,
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count => PC);
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count => PC);
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-- The watchdog and its access to the main databus
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watchdog_re: bus_access_x16
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watchdog_re: bus_access_x16
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port map ( clk => clk,
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port map ( clk => clk,
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en => watchdog_control(1),
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en => watchdog_control(1),
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dataRead => mainDataBus,
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dataRead => mainDataBus,
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dataWrite => watchdog_rst_value);
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dataWrite => watchdog_rst_value);
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| Line 155... |
Line 163... |
myId => uP_id,
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myId => uP_id,
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watchdog_left => watchdog_left,
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watchdog_left => watchdog_left,
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watchdog_rst_value => watchdog_rst_value,
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watchdog_rst_value => watchdog_rst_value,
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watchdog_rst => watchdog_rst);
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watchdog_rst => watchdog_rst);
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-- The stack
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stack: stack_x16
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stack: stack_x16
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generic map( STACK_SIZE => 8)
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generic map( STACK_SIZE => 8)
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port map( clk => clk,
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port map( clk => clk,
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reset => reset,
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reset => reset,
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dataPort => mainDataBus,
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dataPort => mainDataBus,
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push => stack_control(1),
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push => stack_control(1),
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pop => stack_control(0));
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pop => stack_control(0));
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-- The 4 Registers
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-- The 4 Registers
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R1: bus_register_x16
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R1: bus_register_x16
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port ( clk=>clk ,
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port map ( clk=>clk ,
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re=>register_control(0),
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re=>register_control(0),
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we=>register_control(1),
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we=>register_control(1),
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reset=>reset,
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reset=>reset,
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dataport=> mainDataBus);
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dataport=> mainDataBus);
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R2: bus_register_x16
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R2: bus_register_x16
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port ( clk=>clk ,
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port map ( clk=>clk ,
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re=>register_control(2),
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re=>register_control(2),
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we=>register_control(3),
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we=>register_control(3),
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reset=>reset,
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reset=>reset,
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dataport=> mainDataBus);
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dataport=> mainDataBus);
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R3: bus_register_x16
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R3: bus_register_x16
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port ( clk=>clk ,
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port map ( clk=>clk ,
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re=>register_control(4),
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re=>register_control(4),
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we=>register_control(5),
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we=>register_control(5),
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reset=>reset,
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reset=>reset,
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dataport=> mainDataBus);
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dataport=> mainDataBus);
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R4: bus_register_x16
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R4: bus_register_x16
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port ( clk=>clk ,
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port map ( clk=>clk ,
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re=>register_control(6),
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re=>register_control(6),
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we=>register_control(7),
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we=>register_control(7),
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reset=>reset,
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reset=>reset,
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dataport=> mainDataBus);
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dataport=> mainDataBus);
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-- The ALU
|
-- The ALU
|
alu : ALU
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the_alu : ALU
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port( data1 => dataBus1;
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port map( data1 => dataBus1,
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data2 => dataBus2;
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data2 => dataBus2,
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dataA => accumulator;
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dataA => accumulator,
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op => op;
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op => opCode,
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overflow => overflow);
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overflow => ALUoverflow);
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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