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signal ALUoverflow: std_logic;
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signal ALUoverflow: std_logic;
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signal opCode: ALU_OPCODE;
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signal opCode: ALU_OPCODE;
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-- Control signals (driven by the controler)
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-- Control signals (driven by the controler)
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signal register_control: std_logic_vector(7 downto 0); -- re1 we1 re2 we2 re3 we3 re4 we4
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signal register_control: std_logic_vector(7 downto 0); -- re1 we1 re2 we2 re3 we3 re4 we4
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signal stack_control : std_logic_vector(1 downto 0); -- en push/pop
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signal stack_control : std_logic_vector(1 downto 0); --push pop
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signal PC_control : std_logic;
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signal PC_control : std_logic;
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signal inc_PC: std_logic;
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signal inc_PC: std_logic;
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-- Id signal (driven by the identifier)
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-- Id signal (driven by the identifier)
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signal uP_id: std_logic_vector(7 downto 0);
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signal uP_id: std_logic_vector(7 downto 0);
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port ( clk: in std_logic;
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port ( clk: in std_logic;
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reset: in std_logic;
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reset: in std_logic;
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code: in std_logic_vector(15 downto 0);
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code: in std_logic_vector(15 downto 0);
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opCode: out ALU_OPCODE;
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opCode: out ALU_OPCODE;
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register_control: out std_logic_vector(7 downto 0); -- re1 we1 re2 we2 re3 we3 re4 we4
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register_control: out std_logic_vector(7 downto 0); -- re1 we1 re2 we2 re3 we3 re4 we4
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stack_control : out std_logic_vector(1 downto 0); -- en push/pop
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stack_control : out std_logic_vector(1 downto 0); -- push pop
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PC_control : out std_logic;
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PC_control : out std_logic;
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inc_PC: out std_logic;
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inc_PC: out std_logic;
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watchdog_reset: out std_logic;
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watchdog_reset: out std_logic;
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watchdog_control: out std_logic -- re we
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watchdog_control: out std_logic_vector(1 downto 0) -- re(reset_value) we(left)
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);
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);
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end component;
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end component;
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component binary_counter_x16
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component binary_counter_x16
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port ( clk: in std_logic;
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port ( clk: in std_logic;
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data2 => dataBus2,
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data2 => dataBus2,
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dataA => accumulator,
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dataA => accumulator,
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op => opCode,
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op => opCode,
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overflow => ALUoverflow);
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overflow => ALUoverflow);
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-- Controler
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controler : decoder_controler_x16
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port map( clk=> clk,
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reset=> reset,
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code=> code,
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opCode=> opCode,
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register_control=> register_control, -- re1 we1 re2 we2 re3 we3 re4 we4
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stack_control => stack_control, -- push pop
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PC_control => PC_control,
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inc_PC=> inc_PC,
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watchdog_reset=> watchdog_rst,
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watchdog_control=> watchdog_control -- re(reset_value) we(left)
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);
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end Behavioral;
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end Behavioral;
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