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[/] [distributed_intelligence/] [trunk/] [SRC/] [mini_uP_x16.vhd] - Diff between revs 6 and 7

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Rev 6 Rev 7
Line 102... Line 102...
                                        watchdog_rst_value: in std_logic_vector(15 downto 0);
                                        watchdog_rst_value: in std_logic_vector(15 downto 0);
                                        watchdog_rst: in std_logic);
                                        watchdog_rst: in std_logic);
        end component;
        end component;
 
 
        component bus_access_x16
        component bus_access_x16
                port (  clk: in std_logic;
                port (  en      : in std_logic;
                                        en      : in std_logic;
 
                                        dataWrite: out std_logic_vector(15 downto 0);
                                        dataWrite: out std_logic_vector(15 downto 0);
                                        dataRead : in std_logic_vector(15 downto 0));
                                        dataRead : in std_logic_vector(15 downto 0));
        end component;
        end component;
 
 
        component bus_register_x16
        component bus_register_x16
Line 143... Line 142...
                                                set_value => mainDataBus,
                                                set_value => mainDataBus,
                                                count => PC);
                                                count => PC);
 
 
        -- The watchdog and its access to the main databus
        -- The watchdog and its access to the main databus
        watchdog_re: bus_access_x16
        watchdog_re: bus_access_x16
                port map (      clk => clk,
                port map (      en      => watchdog_control(1),
                                                en      => watchdog_control(1),
 
                                                dataRead => mainDataBus,
                                                dataRead => mainDataBus,
                                                dataWrite => watchdog_rst_value);
                                                dataWrite => watchdog_rst_value);
 
 
        watchdog_we: bus_access_x16
        watchdog_we: bus_access_x16
                port map (      clk => clk,
                port map (      en      => watchdog_control(0),
                                                en      => watchdog_control(0),
 
                                                dataRead => watchdog_left,
                                                dataRead => watchdog_left,
                                                dataWrite => mainDataBus);
                                                dataWrite => mainDataBus);
 
 
        watchdog_id: watchdog_identifier_x16
        watchdog_id: watchdog_identifier_x16
                port map(       clk => clk,
                port map(       clk => clk,
Line 203... Line 200...
                                                we=>register_control(7),
                                                we=>register_control(7),
                                                reset=>reset,
                                                reset=>reset,
                                                dataport=> mainDataBus);
                                                dataport=> mainDataBus);
 
 
        -- The ALU                                                      
        -- The ALU                                                      
        the_alu : ALU
        arith_logic_unit : ALU
                port map(       data1 => dataBus1,
                port map(       data1 => dataBus1,
                                                data2 => dataBus2,
                                                data2 => dataBus2,
                                                dataA => accumulator,
                                                dataA => accumulator,
                                                op => opCode,
                                                op => opCode,
                                                overflow => ALUoverflow);
                                                overflow => ALUoverflow);

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