| Line 56... |
Line 56... |
reg [7:0] ReadDataYdc;
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reg [7:0] ReadDataYdc;
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reg [7:0] ReadDataYac;
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reg [7:0] ReadDataYac;
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reg [7:0] ReadDataCdc;
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reg [7:0] ReadDataCdc;
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reg [7:0] ReadDataCac;
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reg [7:0] ReadDataCac;
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|
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reg [7:0] ReadData;
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wire [7:0] ReadData;
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|
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// RAM
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// RAM
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(DataInEnable ==1'b1 & DataInColor ==2'b00) begin
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if(DataInEnable ==1'b1 & DataInColor ==2'b00) begin
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DHT_Ydc[DataInCount[3:0]] <= DataIn;
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DHT_Ydc[DataInCount[3:0]] <= DataIn;
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| Line 82... |
Line 82... |
ReadDataCdc <= DHT_Cdc[TableNumber[3:0]];
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ReadDataCdc <= DHT_Cdc[TableNumber[3:0]];
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ReadDataCac <= DHT_Cac[TableNumber];
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ReadDataCac <= DHT_Cac[TableNumber];
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end // always @ (posedge clk or negedge rst)
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end // always @ (posedge clk or negedge rst)
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|
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// Selector
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// Selector
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always @(*) begin
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/*
|
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always @(*) begin
|
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case (ColorNumber)
|
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2'b00: ReadData <= ReadDataYdc;
|
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2'b01: ReadData <= ReadDataYac;
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2'b10: ReadData <= ReadDataCdc;
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2'b11: ReadData <= ReadDataCac;
|
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endcase // case(ColorNumber)
|
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end
|
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*/
|
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function [7:0] ReadDataSel;
|
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input [1:0] ColorNumber;
|
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input [7:0] ReadDataYdc;
|
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input [7:0] ReadDataYac;
|
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input [7:0] ReadDataCdc;
|
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input [7:0] ReadDataCac;
|
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begin
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case (ColorNumber)
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case (ColorNumber)
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2'b00: ReadData <= ReadDataYdc;
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2'b00: ReadDataSel = ReadDataYdc;
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2'b01: ReadData <= ReadDataYac;
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2'b01: ReadDataSel = ReadDataYac;
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2'b10: ReadData <= ReadDataCdc;
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2'b10: ReadDataSel = ReadDataCdc;
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2'b11: ReadData <= ReadDataCac;
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2'b11: ReadDataSel = ReadDataCac;
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endcase // case(ColorNumber)
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endcase
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end
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end
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endfunction
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|
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assign ReadData = ReadDataSel(ColorNumber, ReadDataYdc, ReadDataYac, ReadDataCdc, ReadDataCac);
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|
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assign ZeroTable = ReadData[7:4];
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assign ZeroTable = ReadData[7:4];
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assign WidhtTable = ReadData[3:0];
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assign WidhtTable = ReadData[3:0];
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|
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endmodule // jpeg_dht
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endmodule // jpeg_dht
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