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// Project : JPEG Decoder
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// Project : JPEG Decoder
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// Belong to :
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// Belong to :
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// Author : H.Ishihara
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// Author : H.Ishihara
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// E-Mail : hidemi@sweetcafe.jp
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// E-Mail : hidemi@sweetcafe.jp
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// HomePage : http://www.sweetcafe.jp/
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// HomePage : http://www.sweetcafe.jp/
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// Date : 2006/10/01
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// Date : 2008/03/19
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// Rev. : 1.1
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// Rev. : 2.00
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Rev. Date Description
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// Rev. Date Description
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// 1.01 2006/10/01 1st Release
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// 1.01 2006/10/01 1st Release
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//---------------------------------------------------------------------------
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// 2.00 2008/03/19 Replace to RAM from D-FF
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// $Id:
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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`timescale 1ps / 1ps
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`timescale 1ps / 1ps
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module jpeg_idctb
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module jpeg_idctb(
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(
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rst,
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rst,
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clk,
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clk,
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DataInit,
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DataInEnable,
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DataInEnable,
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DataInPage,
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DataInPage,
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DataInCount,
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DataInCount,
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DataInIdle,
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DataInIdle,
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Data0In,
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DataInA,
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Data1In,
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DataInB,
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DataOutEnable,
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DataOutEnable,
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DataOutSel,
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DataOutRead,
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Data00Out,
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DataOutAddress,
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Data01Out,
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DataOutA,
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Data02Out,
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DataOutB
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Data03Out,
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Data04Out,
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Data05Out,
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Data06Out,
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Data07Out,
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Data08Out,
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Data09Out,
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Data10Out,
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Data11Out,
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Data12Out,
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Data13Out,
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Data14Out,
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Data15Out,
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Data16Out,
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Data17Out,
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Data18Out,
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Data19Out,
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Data20Out,
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Data21Out,
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Data22Out,
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Data23Out,
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Data24Out,
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Data25Out,
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Data26Out,
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Data27Out,
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Data28Out,
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Data29Out,
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Data30Out,
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Data31Out,
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Data32Out,
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Data33Out,
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Data34Out,
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Data35Out,
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Data36Out,
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Data37Out,
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Data38Out,
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Data39Out,
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Data40Out,
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Data41Out,
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Data42Out,
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Data43Out,
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Data44Out,
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Data45Out,
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Data46Out,
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Data47Out,
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Data48Out,
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Data49Out,
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Data50Out,
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Data51Out,
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Data52Out,
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Data53Out,
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Data54Out,
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Data55Out,
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Data56Out,
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Data57Out,
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Data58Out,
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Data59Out,
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Data60Out,
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Data61Out,
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Data62Out,
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Data63Out,
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BankARelease,
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BankBRelease
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);
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);
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input clk;
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input clk;
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input rst;
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input rst;
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input DataInit;
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input DataInEnable;
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input DataInEnable;
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input [2:0] DataInPage;
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input [2:0] DataInPage;
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input [1:0] DataInCount;
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input [1:0] DataInCount;
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output DataInIdle;
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output DataInIdle;
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input [15:0] Data0In;
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input [15:0] DataInA;
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input [15:0] Data1In;
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input [15:0] DataInB;
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output DataOutEnable;
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output DataOutEnable;
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input DataOutSel;
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input DataOutRead;
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output [15:0] Data00Out;
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input [4:0] DataOutAddress;
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output [15:0] Data01Out;
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output [15:0] DataOutA;
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output [15:0] Data02Out;
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output [15:0] DataOutB;
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output [15:0] Data03Out;
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output [15:0] Data04Out;
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output [15:0] Data05Out;
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output [15:0] Data06Out;
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output [15:0] Data07Out;
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output [15:0] Data08Out;
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output [15:0] Data09Out;
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output [15:0] Data10Out;
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output [15:0] Data11Out;
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output [15:0] Data12Out;
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output [15:0] Data13Out;
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output [15:0] Data14Out;
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output [15:0] Data15Out;
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output [15:0] Data16Out;
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output [15:0] Data17Out;
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output [15:0] Data18Out;
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output [15:0] Data19Out;
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output [15:0] Data20Out;
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output [15:0] Data21Out;
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output [15:0] Data22Out;
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output [15:0] Data23Out;
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output [15:0] Data24Out;
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output [15:0] Data25Out;
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output [15:0] Data26Out;
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output [15:0] Data27Out;
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output [15:0] Data28Out;
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output [15:0] Data29Out;
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output [15:0] Data30Out;
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output [15:0] Data31Out;
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output [15:0] Data32Out;
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output [15:0] Data33Out;
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output [15:0] Data34Out;
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output [15:0] Data35Out;
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output [15:0] Data36Out;
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output [15:0] Data37Out;
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output [15:0] Data38Out;
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output [15:0] Data39Out;
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output [15:0] Data40Out;
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output [15:0] Data41Out;
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output [15:0] Data42Out;
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output [15:0] Data43Out;
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output [15:0] Data44Out;
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output [15:0] Data45Out;
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output [15:0] Data46Out;
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output [15:0] Data47Out;
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output [15:0] Data48Out;
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output [15:0] Data49Out;
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output [15:0] Data50Out;
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output [15:0] Data51Out;
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output [15:0] Data52Out;
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output [15:0] Data53Out;
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output [15:0] Data54Out;
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output [15:0] Data55Out;
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output [15:0] Data56Out;
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output [15:0] Data57Out;
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output [15:0] Data58Out;
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output [15:0] Data59Out;
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output [15:0] Data60Out;
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output [15:0] Data61Out;
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output [15:0] Data62Out;
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output [15:0] Data63Out;
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input BankARelease;
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input BankBRelease;
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reg BankAEnable;
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reg BankBEnable;
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reg DataInBank;
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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BankAEnable <= 1'b0;
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BankBEnable <= 1'b0;
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DataInBank <= 1'b0;
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end else begin
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if(BankAEnable == 1'b0 & DataInBank == 1'b0) begin
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if(DataInEnable == 1'b1 &
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DataInPage == 3'd7 & DataInCount == 2'd3) begin
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BankAEnable <= 1'b1;
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end
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end else begin
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if(BankARelease == 1'b1) begin
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BankAEnable <= 1'b0;
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end
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end
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if(BankBEnable == 1'b0 & DataInBank == 1'b1) begin
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if(DataInEnable == 1'b1 &
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DataInPage == 3'd7 & DataInCount == 2'd3) begin
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BankBEnable <= 1'b1;
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end
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end else begin
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if(BankBRelease == 1'b1) begin
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BankBEnable <= 1'b0;
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end
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end
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if(DataInEnable == 1'b1 &
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DataInPage == 3'd7 & DataInCount == 2'd3) begin
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DataInBank <= ~DataInBank;
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end
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end // else: !if(!rst)
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end // always @ (posedge clk or negedge rst)
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assign DataInIdle = BankAEnable == 1'b0 | BankBEnable == 1'b0;
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wire [4:0] DataInAddress;
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reg [1:0] WriteBank, ReadBank;
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assign DataOutEnable = DataInEnable == 1'b1 & DataInPage == 3'b111 &
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assign DataInAddress = {DataInPage, DataInCount};
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DataInCount == 2'b11;
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reg [15:0] BankAReg [0:63];
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// Bank
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always @(posedge clk or negedge rst) begin
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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if(!rst) begin
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BankAReg[0] <= 12'h000;
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WriteBank <= 2'd0;
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BankAReg[1] <= 12'h000;
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ReadBank <= 2'd0;
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BankAReg[2] <= 12'h000;
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end else begin
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BankAReg[3] <= 12'h000;
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if(DataInit) begin
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BankAReg[4] <= 12'h000;
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WriteBank <= 2'd0;
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BankAReg[5] <= 12'h000;
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end else if(DataInEnable && (DataInAddress == 5'h1F)) begin
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BankAReg[6] <= 12'h000;
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WriteBank <= WriteBank + 2'd1;
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BankAReg[7] <= 12'h000;
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end
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BankAReg[8] <= 12'h000;
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if(DataInit) begin
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BankAReg[9] <= 12'h000;
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ReadBank <= 2'd0;
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BankAReg[10] <= 12'h000;
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end else if(DataOutRead && (DataOutAddress == 5'h1F)) begin
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BankAReg[11] <= 12'h000;
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ReadBank <= ReadBank + 2'd1;
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BankAReg[12] <= 12'h000;
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end
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BankAReg[13] <= 12'h000;
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end
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BankAReg[14] <= 12'h000;
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end
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BankAReg[15] <= 12'h000;
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BankAReg[16] <= 12'h000;
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wire [5:0] WriteQueryA, WriteQueryB;
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BankAReg[17] <= 12'h000;
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BankAReg[18] <= 12'h000;
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// Make a Write Address
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BankAReg[19] <= 12'h000;
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function [5:0] F_WriteQueryA;
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BankAReg[20] <= 12'h000;
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input [4:0] Count;
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BankAReg[21] <= 12'h000;
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case(Count)
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BankAReg[22] <= 12'h000;
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5'd0: F_WriteQueryA = {1'd0, 5'd0}; // 0
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BankAReg[23] <= 12'h000;
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5'd1: F_WriteQueryA = {1'd0, 5'd4}; // 1
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BankAReg[24] <= 12'h000;
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5'd2: F_WriteQueryA = {1'd0, 5'd8}; // 2
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BankAReg[25] <= 12'h000;
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5'd3: F_WriteQueryA = {1'd0, 5'd12}; // 3
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BankAReg[26] <= 12'h000;
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5'd4: F_WriteQueryA = {1'd0, 5'd2}; // 8
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BankAReg[27] <= 12'h000;
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5'd5: F_WriteQueryA = {1'd0, 5'd6}; // 9
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BankAReg[28] <= 12'h000;
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5'd6: F_WriteQueryA = {1'd0, 5'd10}; // 10
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BankAReg[29] <= 12'h000;
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5'd7: F_WriteQueryA = {1'd0, 5'd14}; // 11
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BankAReg[30] <= 12'h000;
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5'd8: F_WriteQueryA = {1'd0, 5'd1}; // 16
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BankAReg[31] <= 12'h000;
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5'd9: F_WriteQueryA = {1'd0, 5'd5}; // 17
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BankAReg[32] <= 12'h000;
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5'd10: F_WriteQueryA = {1'd0, 5'd9}; // 18
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BankAReg[33] <= 12'h000;
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5'd11: F_WriteQueryA = {1'd0, 5'd13}; // 19
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BankAReg[34] <= 12'h000;
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5'd12: F_WriteQueryA = {1'd1, 5'd3}; // 24
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BankAReg[35] <= 12'h000;
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5'd13: F_WriteQueryA = {1'd1, 5'd7}; // 25
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BankAReg[36] <= 12'h000;
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5'd14: F_WriteQueryA = {1'd1, 5'd11}; // 26
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BankAReg[37] <= 12'h000;
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5'd15: F_WriteQueryA = {1'd1, 5'd15}; // 27
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BankAReg[38] <= 12'h000;
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5'd16: F_WriteQueryA = {1'd1, 5'd0}; // 32
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BankAReg[39] <= 12'h000;
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5'd17: F_WriteQueryA = {1'd1, 5'd4}; // 33
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BankAReg[40] <= 12'h000;
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5'd18: F_WriteQueryA = {1'd1, 5'd8}; // 34
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BankAReg[41] <= 12'h000;
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5'd19: F_WriteQueryA = {1'd1, 5'd12}; // 35
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BankAReg[42] <= 12'h000;
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5'd20: F_WriteQueryA = {1'd0, 5'd3}; // 40
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BankAReg[43] <= 12'h000;
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5'd21: F_WriteQueryA = {1'd0, 5'd7}; // 41
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BankAReg[44] <= 12'h000;
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5'd22: F_WriteQueryA = {1'd0, 5'd11}; // 42
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BankAReg[45] <= 12'h000;
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5'd23: F_WriteQueryA = {1'd0, 5'd15}; // 43
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BankAReg[46] <= 12'h000;
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5'd24: F_WriteQueryA = {1'd1, 5'd1}; // 48
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BankAReg[47] <= 12'h000;
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5'd25: F_WriteQueryA = {1'd1, 5'd5}; // 49
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BankAReg[48] <= 12'h000;
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5'd26: F_WriteQueryA = {1'd1, 5'd9}; // 50
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BankAReg[49] <= 12'h000;
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5'd27: F_WriteQueryA = {1'd1, 5'd13}; // 51
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BankAReg[50] <= 12'h000;
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5'd28: F_WriteQueryA = {1'd1, 5'd2}; // 56
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BankAReg[51] <= 12'h000;
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5'd29: F_WriteQueryA = {1'd1, 5'd6}; // 57
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BankAReg[52] <= 12'h000;
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5'd30: F_WriteQueryA = {1'd1, 5'd10}; // 58
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BankAReg[53] <= 12'h000;
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5'd31: F_WriteQueryA = {1'd1, 5'd14}; // 59
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BankAReg[54] <= 12'h000;
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endcase
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BankAReg[55] <= 12'h000;
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endfunction
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BankAReg[56] <= 12'h000;
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BankAReg[57] <= 12'h000;
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function [5:0] F_WriteQueryB;
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BankAReg[58] <= 12'h000;
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input [4:0] Count;
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BankAReg[59] <= 12'h000;
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case(Count)
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BankAReg[60] <= 12'h000;
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5'd0: F_WriteQueryB = {1'd1, 5'd28}; // 7
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BankAReg[61] <= 12'h000;
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5'd1: F_WriteQueryB = {1'd1, 5'd24}; // 6
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BankAReg[62] <= 12'h000;
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5'd2: F_WriteQueryB = {1'd1, 5'd20}; // 5
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BankAReg[63] <= 12'h000;
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5'd3: F_WriteQueryB = {1'd1, 5'd16}; // 4
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end else begin // if (!rst)
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5'd4: F_WriteQueryB = {1'd1, 5'd30}; // 15
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if(DataInEnable == 1'b1 & DataInBank == 1'b0) begin
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5'd5: F_WriteQueryB = {1'd1, 5'd26}; // 14
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case(DataInPage)
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5'd6: F_WriteQueryB = {1'd1, 5'd22}; // 13
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3'd0: begin
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5'd7: F_WriteQueryB = {1'd1, 5'd18}; // 12
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case(DataInCount)
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5'd8: F_WriteQueryB = {1'd1, 5'd29}; // 23
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2'd0: begin
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5'd9: F_WriteQueryB = {1'd1, 5'd25}; // 22
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BankAReg[0] <= Data0In;
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5'd10: F_WriteQueryB = {1'd1, 5'd21}; // 21
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BankAReg[7] <= Data1In;
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5'd11: F_WriteQueryB = {1'd1, 5'd17}; // 20
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end
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5'd12: F_WriteQueryB = {1'd0, 5'd31}; // 31
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2'd1: begin
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5'd13: F_WriteQueryB = {1'd0, 5'd27}; // 30
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BankAReg[1] <= Data0In;
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5'd14: F_WriteQueryB = {1'd0, 5'd23}; // 29
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BankAReg[6] <= Data1In;
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5'd15: F_WriteQueryB = {1'd0, 5'd19}; // 28
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end
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5'd16: F_WriteQueryB = {1'd0, 5'd28}; // 39
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2'd2: begin
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5'd17: F_WriteQueryB = {1'd0, 5'd24}; // 38
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BankAReg[2] <= Data0In;
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5'd18: F_WriteQueryB = {1'd0, 5'd20}; // 37
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BankAReg[5] <= Data1In;
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5'd19: F_WriteQueryB = {1'd0, 5'd16}; // 36
|
end
|
5'd20: F_WriteQueryB = {1'd1, 5'd31}; // 47
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2'd3: begin
|
5'd21: F_WriteQueryB = {1'd1, 5'd27}; // 46
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BankAReg[3] <= Data0In;
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5'd22: F_WriteQueryB = {1'd1, 5'd23}; // 45
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BankAReg[4] <= Data1In;
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5'd23: F_WriteQueryB = {1'd1, 5'd19}; // 44
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end
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5'd24: F_WriteQueryB = {1'd0, 5'd29}; // 55
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endcase // case(DataInCount)
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5'd25: F_WriteQueryB = {1'd0, 5'd25}; // 54
|
end // case: 3'd0
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5'd26: F_WriteQueryB = {1'd0, 5'd21}; // 53
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3'd1: begin
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5'd27: F_WriteQueryB = {1'd0, 5'd17}; // 52
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case(DataInCount)
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5'd28: F_WriteQueryB = {1'd0, 5'd30}; // 63
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2'd0: begin
|
5'd29: F_WriteQueryB = {1'd0, 5'd26}; // 62
|
BankAReg[8] <= Data0In;
|
5'd30: F_WriteQueryB = {1'd0, 5'd22}; // 61
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BankAReg[15] <= Data1In;
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5'd31: F_WriteQueryB = {1'd0, 5'd18}; // 60
|
end
|
endcase
|
2'd1: begin
|
endfunction
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BankAReg[9] <= Data0In;
|
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BankAReg[14] <= Data1In;
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assign WriteQueryA = F_WriteQueryA(DataInAddress);
|
end
|
assign WriteQueryB = F_WriteQueryB(DataInAddress);
|
2'd2: begin
|
|
BankAReg[10] <= Data0In;
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// RAM(16bit x 32word x 2Bank)
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BankAReg[13] <= Data1In;
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reg [15:0] MemoryA [0:127];
|
end
|
reg [15:0] MemoryB [0:127];
|
2'd3: begin
|
|
BankAReg[11] <= Data0In;
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wire [6:0] WriteAddressA, WriteAddressB;
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BankAReg[12] <= Data1In;
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wire [15:0] WriteDataA, WriteDataB;
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end
|
|
endcase // case(DataInCount)
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assign WriteAddressA = {WriteBank, (WriteQueryA[5])?WriteQueryB[4:0]:WriteQueryA[4:0]};
|
end // case: 3'd1
|
assign WriteAddressB = {WriteBank, (WriteQueryB[5])?WriteQueryB[4:0]:WriteQueryA[4:0]};
|
3'd2: begin
|
|
case(DataInCount)
|
assign WriteDataA = (WriteQueryA[5])?DataInB:DataInA;
|
2'd0: begin
|
assign WriteDataB = (WriteQueryB[5])?DataInB:DataInA;
|
BankAReg[16] <= Data0In;
|
|
BankAReg[23] <= Data1In;
|
// Port A(Write Only)
|
end
|
always @(posedge clk) begin
|
2'd1: begin
|
if(DataInEnable) MemoryA[WriteAddressA] <= WriteDataA;
|
BankAReg[17] <= Data0In;
|
if(DataInEnable) MemoryB[WriteAddressB] <= WriteDataB;
|
BankAReg[22] <= Data1In;
|
end
|
end
|
|
2'd2: begin
|
reg [15:0] RegMemoryA, RegMemoryB;
|
BankAReg[18] <= Data0In;
|
|
BankAReg[21] <= Data1In;
|
// Port B(Read/Wirte)
|
end
|
always @(posedge clk) begin
|
2'd3: begin
|
RegMemoryA <= MemoryA[{ReadBank, DataOutAddress}];
|
BankAReg[19] <= Data0In;
|
RegMemoryB <= MemoryB[{ReadBank, DataOutAddress}];
|
BankAReg[20] <= Data1In;
|
end
|
end
|
|
endcase // case(DataInCount)
|
assign DataOutEnable = (WriteBank != ReadBank);
|
end // case: 3'd2
|
assign DataOutA = (DataOutAddress[4])?RegMemoryB:RegMemoryA;
|
3'd3: begin
|
assign DataOutB = (DataOutAddress[4])?RegMemoryA:RegMemoryB;
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankAReg[24] <= Data0In;
|
|
BankAReg[31] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankAReg[25] <= Data0In;
|
|
BankAReg[30] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankAReg[26] <= Data0In;
|
|
BankAReg[29] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankAReg[27] <= Data0In;
|
|
BankAReg[28] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd3
|
|
3'd4: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankAReg[32] <= Data0In;
|
|
BankAReg[39] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankAReg[33] <= Data0In;
|
|
BankAReg[38] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankAReg[34] <= Data0In;
|
|
BankAReg[37] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankAReg[35] <= Data0In;
|
|
BankAReg[36] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd4
|
|
3'd5: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankAReg[40] <= Data0In;
|
|
BankAReg[47] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankAReg[41] <= Data0In;
|
|
BankAReg[46] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankAReg[42] <= Data0In;
|
|
BankAReg[45] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankAReg[43] <= Data0In;
|
|
BankAReg[44] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd5
|
|
3'd6: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankAReg[48] <= Data0In;
|
|
BankAReg[55] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankAReg[49] <= Data0In;
|
|
BankAReg[54] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankAReg[50] <= Data0In;
|
|
BankAReg[53] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankAReg[51] <= Data0In;
|
|
BankAReg[52] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd6
|
|
3'd7: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankAReg[56] <= Data0In;
|
|
BankAReg[63] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankAReg[57] <= Data0In;
|
|
BankAReg[62] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankAReg[58] <= Data0In;
|
|
BankAReg[61] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankAReg[59] <= Data0In;
|
|
BankAReg[60] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd7
|
|
endcase // case(DataInPage)
|
|
end // if (DataInEnable == 1'b1 & DataInBank == 1'b0)
|
|
end // else: !if(!rst)
|
|
end // always @ (posedge clk or negedge rst)
|
|
|
|
reg [15:0] BankBReg [0:63];
|
|
|
|
always @(posedge clk or negedge rst) begin
|
|
if(!rst) begin
|
|
BankBReg[0] <= 12'h000;
|
|
BankBReg[1] <= 12'h000;
|
|
BankBReg[2] <= 12'h000;
|
|
BankBReg[3] <= 12'h000;
|
|
BankBReg[4] <= 12'h000;
|
|
BankBReg[5] <= 12'h000;
|
|
BankBReg[6] <= 12'h000;
|
|
BankBReg[7] <= 12'h000;
|
|
BankBReg[8] <= 12'h000;
|
|
BankBReg[9] <= 12'h000;
|
|
BankBReg[10] <= 12'h000;
|
|
BankBReg[11] <= 12'h000;
|
|
BankBReg[12] <= 12'h000;
|
|
BankBReg[13] <= 12'h000;
|
|
BankBReg[14] <= 12'h000;
|
|
BankBReg[15] <= 12'h000;
|
|
BankBReg[16] <= 12'h000;
|
|
BankBReg[17] <= 12'h000;
|
|
BankBReg[18] <= 12'h000;
|
|
BankBReg[19] <= 12'h000;
|
|
BankBReg[20] <= 12'h000;
|
|
BankBReg[21] <= 12'h000;
|
|
BankBReg[22] <= 12'h000;
|
|
BankBReg[23] <= 12'h000;
|
|
BankBReg[24] <= 12'h000;
|
|
BankBReg[25] <= 12'h000;
|
|
BankBReg[26] <= 12'h000;
|
|
BankBReg[27] <= 12'h000;
|
|
BankBReg[28] <= 12'h000;
|
|
BankBReg[29] <= 12'h000;
|
|
BankBReg[30] <= 12'h000;
|
|
BankBReg[31] <= 12'h000;
|
|
BankBReg[32] <= 12'h000;
|
|
BankBReg[33] <= 12'h000;
|
|
BankBReg[34] <= 12'h000;
|
|
BankBReg[35] <= 12'h000;
|
|
BankBReg[36] <= 12'h000;
|
|
BankBReg[37] <= 12'h000;
|
|
BankBReg[38] <= 12'h000;
|
|
BankBReg[39] <= 12'h000;
|
|
BankBReg[40] <= 12'h000;
|
|
BankBReg[41] <= 12'h000;
|
|
BankBReg[42] <= 12'h000;
|
|
BankBReg[43] <= 12'h000;
|
|
BankBReg[44] <= 12'h000;
|
|
BankBReg[45] <= 12'h000;
|
|
BankBReg[46] <= 12'h000;
|
|
BankBReg[47] <= 12'h000;
|
|
BankBReg[48] <= 12'h000;
|
|
BankBReg[49] <= 12'h000;
|
|
BankBReg[50] <= 12'h000;
|
|
BankBReg[51] <= 12'h000;
|
|
BankBReg[52] <= 12'h000;
|
|
BankBReg[53] <= 12'h000;
|
|
BankBReg[54] <= 12'h000;
|
|
BankBReg[55] <= 12'h000;
|
|
BankBReg[56] <= 12'h000;
|
|
BankBReg[57] <= 12'h000;
|
|
BankBReg[58] <= 12'h000;
|
|
BankBReg[59] <= 12'h000;
|
|
BankBReg[60] <= 12'h000;
|
|
BankBReg[61] <= 12'h000;
|
|
BankBReg[62] <= 12'h000;
|
|
BankBReg[63] <= 12'h000;
|
|
end else begin // if (!rst)
|
|
if(DataInEnable == 1'b1 & DataInBank == 1'b1) begin
|
|
case(DataInPage)
|
|
3'd0: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankBReg[0] <= Data0In;
|
|
BankBReg[7] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankBReg[1] <= Data0In;
|
|
BankBReg[6] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankBReg[2] <= Data0In;
|
|
BankBReg[5] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankBReg[3] <= Data0In;
|
|
BankBReg[4] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd0
|
|
3'd1: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankBReg[8] <= Data0In;
|
|
BankBReg[15] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankBReg[9] <= Data0In;
|
|
BankBReg[14] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankBReg[10] <= Data0In;
|
|
BankBReg[13] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankBReg[11] <= Data0In;
|
|
BankBReg[12] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd1
|
|
3'd2: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankBReg[16] <= Data0In;
|
|
BankBReg[23] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankBReg[17] <= Data0In;
|
|
BankBReg[22] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankBReg[18] <= Data0In;
|
|
BankBReg[21] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankBReg[19] <= Data0In;
|
|
BankBReg[20] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd2
|
|
3'd3: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankBReg[24] <= Data0In;
|
|
BankBReg[31] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankBReg[25] <= Data0In;
|
|
BankBReg[30] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankBReg[26] <= Data0In;
|
|
BankBReg[29] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankBReg[27] <= Data0In;
|
|
BankBReg[28] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd3
|
|
3'd4: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankBReg[32] <= Data0In;
|
|
BankBReg[39] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankBReg[33] <= Data0In;
|
|
BankBReg[38] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankBReg[34] <= Data0In;
|
|
BankBReg[37] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankBReg[35] <= Data0In;
|
|
BankBReg[36] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd4
|
|
3'd5: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankBReg[40] <= Data0In;
|
|
BankBReg[47] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankBReg[41] <= Data0In;
|
|
BankBReg[46] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankBReg[42] <= Data0In;
|
|
BankBReg[45] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankBReg[43] <= Data0In;
|
|
BankBReg[44] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd5
|
|
3'd6: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankBReg[48] <= Data0In;
|
|
BankBReg[55] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankBReg[49] <= Data0In;
|
|
BankBReg[54] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankBReg[50] <= Data0In;
|
|
BankBReg[53] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankBReg[51] <= Data0In;
|
|
BankBReg[52] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd6
|
|
3'd7: begin
|
|
case(DataInCount)
|
|
2'd0: begin
|
|
BankBReg[56] <= Data0In;
|
|
BankBReg[63] <= Data1In;
|
|
end
|
|
2'd1: begin
|
|
BankBReg[57] <= Data0In;
|
|
BankBReg[62] <= Data1In;
|
|
end
|
|
2'd2: begin
|
|
BankBReg[58] <= Data0In;
|
|
BankBReg[61] <= Data1In;
|
|
end
|
|
2'd3: begin
|
|
BankBReg[59] <= Data0In;
|
|
BankBReg[60] <= Data1In;
|
|
end
|
|
endcase // case(DataInCount)
|
|
end // case: 3'd7
|
|
endcase // case(DataInPage)
|
|
end // if (DataInEnable == 1'b1 & DataInBank == 1'b1)
|
|
end // else: !if(!rst)
|
|
end // always @ (posedge clk or negedge rst)
|
|
|
|
assign Data00Out = (DataOutSel)?BankBReg[00]:BankAReg[00];
|
|
assign Data01Out = (DataOutSel)?BankBReg[08]:BankAReg[08];
|
|
assign Data02Out = (DataOutSel)?BankBReg[16]:BankAReg[16];
|
|
assign Data03Out = (DataOutSel)?BankBReg[24]:BankAReg[24];
|
|
assign Data04Out = (DataOutSel)?BankBReg[32]:BankAReg[32];
|
|
assign Data05Out = (DataOutSel)?BankBReg[40]:BankAReg[40];
|
|
assign Data06Out = (DataOutSel)?BankBReg[48]:BankAReg[48];
|
|
assign Data07Out = (DataOutSel)?BankBReg[56]:BankAReg[56];
|
|
assign Data08Out = (DataOutSel)?BankBReg[01]:BankAReg[01];
|
|
assign Data09Out = (DataOutSel)?BankBReg[09]:BankAReg[09];
|
|
assign Data10Out = (DataOutSel)?BankBReg[17]:BankAReg[17];
|
|
assign Data11Out = (DataOutSel)?BankBReg[25]:BankAReg[25];
|
|
assign Data12Out = (DataOutSel)?BankBReg[33]:BankAReg[33];
|
|
assign Data13Out = (DataOutSel)?BankBReg[41]:BankAReg[41];
|
|
assign Data14Out = (DataOutSel)?BankBReg[49]:BankAReg[49];
|
|
assign Data15Out = (DataOutSel)?BankBReg[57]:BankAReg[57];
|
|
assign Data16Out = (DataOutSel)?BankBReg[02]:BankAReg[02];
|
|
assign Data17Out = (DataOutSel)?BankBReg[10]:BankAReg[10];
|
|
assign Data18Out = (DataOutSel)?BankBReg[18]:BankAReg[18];
|
|
assign Data19Out = (DataOutSel)?BankBReg[26]:BankAReg[26];
|
|
assign Data20Out = (DataOutSel)?BankBReg[34]:BankAReg[34];
|
|
assign Data21Out = (DataOutSel)?BankBReg[42]:BankAReg[42];
|
|
assign Data22Out = (DataOutSel)?BankBReg[50]:BankAReg[50];
|
|
assign Data23Out = (DataOutSel)?BankBReg[58]:BankAReg[58];
|
|
assign Data24Out = (DataOutSel)?BankBReg[03]:BankAReg[03];
|
|
assign Data25Out = (DataOutSel)?BankBReg[11]:BankAReg[11];
|
|
assign Data26Out = (DataOutSel)?BankBReg[19]:BankAReg[19];
|
|
assign Data27Out = (DataOutSel)?BankBReg[27]:BankAReg[27];
|
|
assign Data28Out = (DataOutSel)?BankBReg[35]:BankAReg[35];
|
|
assign Data29Out = (DataOutSel)?BankBReg[43]:BankAReg[43];
|
|
assign Data30Out = (DataOutSel)?BankBReg[51]:BankAReg[51];
|
|
assign Data31Out = (DataOutSel)?BankBReg[59]:BankAReg[59];
|
|
assign Data32Out = (DataOutSel)?BankBReg[04]:BankAReg[04];
|
|
assign Data33Out = (DataOutSel)?BankBReg[12]:BankAReg[12];
|
|
assign Data34Out = (DataOutSel)?BankBReg[20]:BankAReg[20];
|
|
assign Data35Out = (DataOutSel)?BankBReg[28]:BankAReg[28];
|
|
assign Data36Out = (DataOutSel)?BankBReg[36]:BankAReg[36];
|
|
assign Data37Out = (DataOutSel)?BankBReg[44]:BankAReg[44];
|
|
assign Data38Out = (DataOutSel)?BankBReg[52]:BankAReg[52];
|
|
assign Data39Out = (DataOutSel)?BankBReg[60]:BankAReg[60];
|
|
assign Data40Out = (DataOutSel)?BankBReg[05]:BankAReg[05];
|
|
assign Data41Out = (DataOutSel)?BankBReg[13]:BankAReg[13];
|
|
assign Data42Out = (DataOutSel)?BankBReg[21]:BankAReg[21];
|
|
assign Data43Out = (DataOutSel)?BankBReg[29]:BankAReg[29];
|
|
assign Data44Out = (DataOutSel)?BankBReg[37]:BankAReg[37];
|
|
assign Data45Out = (DataOutSel)?BankBReg[45]:BankAReg[45];
|
|
assign Data46Out = (DataOutSel)?BankBReg[53]:BankAReg[53];
|
|
assign Data47Out = (DataOutSel)?BankBReg[61]:BankAReg[61];
|
|
assign Data48Out = (DataOutSel)?BankBReg[06]:BankAReg[06];
|
|
assign Data49Out = (DataOutSel)?BankBReg[14]:BankAReg[14];
|
|
assign Data50Out = (DataOutSel)?BankBReg[22]:BankAReg[22];
|
|
assign Data51Out = (DataOutSel)?BankBReg[30]:BankAReg[30];
|
|
assign Data52Out = (DataOutSel)?BankBReg[38]:BankAReg[38];
|
|
assign Data53Out = (DataOutSel)?BankBReg[46]:BankAReg[46];
|
|
assign Data54Out = (DataOutSel)?BankBReg[54]:BankAReg[54];
|
|
assign Data55Out = (DataOutSel)?BankBReg[62]:BankAReg[62];
|
|
assign Data56Out = (DataOutSel)?BankBReg[07]:BankAReg[07];
|
|
assign Data57Out = (DataOutSel)?BankBReg[15]:BankAReg[15];
|
|
assign Data58Out = (DataOutSel)?BankBReg[23]:BankAReg[23];
|
|
assign Data59Out = (DataOutSel)?BankBReg[31]:BankAReg[31];
|
|
assign Data60Out = (DataOutSel)?BankBReg[39]:BankAReg[39];
|
|
assign Data61Out = (DataOutSel)?BankBReg[47]:BankAReg[47];
|
|
assign Data62Out = (DataOutSel)?BankBReg[55]:BankAReg[55];
|
|
assign Data63Out = (DataOutSel)?BankBReg[63]:BankAReg[63];
|
|
|
|
endmodule // jpeg_idctb
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
