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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// File Name : jpeg_regdata.v
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// File Name : jpeg_regdata.v
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// Module Name : jpeg_regdata
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// Module Name : jpeg_regdata
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// Description : get Data
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// Description : Get Data
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// Project : JPEG Decoder
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// Project : JPEG Decoder
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// Belong to :
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// Belong to :
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// Author : H.Ishihara
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// Author : H.Ishihara
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// E-Mail : hidemi@sweetcafe.jp
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// E-Mail : hidemi@sweetcafe.jp
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// HomePage : http://www.sweetcafe.jp/
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// HomePage : http://www.sweetcafe.jp/
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// Date : 2007/04/11
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// Date : 2008/02/27
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// Rev. : 1.03
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// Rev. : 2.00
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Rev. Date Description
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// Rev. Date Description
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// 1.01 2006/10/01 1st Release
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// 1.01 2006/10/01 1st Release
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// 1.02 2006/10/04 Remove a RegEnd register.
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// 1.02 2006/10/04 Remove a RegEnd register.
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// When reset, clear on OutEnable,PreEnable,DataOut registers.
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// When reset, clear on OutEnable,PreEnable,DataOut registers.
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// Remove some comments.
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// Remove some comments.
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// 1.03 2007/04/11 Don't OutEnable, ImageEnable == 1 and DataOut == 0xFFD9XXXX
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// 1.03 2007/04/11 Don't OutEnable, ImageEnable == 1 and DataOut == 0xFFD9XXXX
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// Stop ReadEnable with DataEnd(after 0xFFD9 of ImageData)
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// Stop ReadEnable with DataEnd(after 0xFFD9 of ImageData)
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//---------------------------------------------------------------------------
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// 1.04 2007/10/16 Modify (RegData[31:0] == 0xFF00FF00) process
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// $Id:
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// not convert 0xFF00 -> 0xFF after convert [7:0] == 0xFF
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// 2.00 2008/02/27 Modify RegValid, when ImageEnable == 1 then RegWidth > 64
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// when ImageEnable == 0 then RegWidth > 32
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// Add SliceData Pattern
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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`timescale 1ps / 1ps
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`timescale 1ps / 1ps
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module jpeg_regdata(
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module jpeg_regdata(
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rst,
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rst,
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input UseByte;
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input UseByte;
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input UseWord;
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input UseWord;
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wire RegValid;
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wire RegValid;
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reg [95:0] RegData;
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reg [95:0] RegData;
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reg [7:0] RegWidth;
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reg [6:0] RegWidth;
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reg CheckMode;
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reg DataEnd;
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reg DataEnd;
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assign RegValid = RegWidth > 64;
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assign RegValid = (ImageEnable)?(RegWidth > 7'd64):(RegWidth > 7'd32);
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assign DataInRead = RegValid == 1'b0 & DataInEnable == 1'b1;
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assign DataInRead = ((RegValid == 1'b0) & (DataInEnable == 1'b1) & (DataEnd == 1'b0));
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always @(posedge clk or negedge rst) begin
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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if(!rst) begin
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RegData <= 96'd0;
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RegData <= 96'd0;
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RegWidth <= 8'h00;
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RegWidth <= 7'd0;
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CheckMode <= 1'b0;
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end else begin
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end else begin
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if(RegValid == 1'b0 & (DataInEnable == 1'b1 | DataEnd == 1'b1)) begin
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if(DataEnd == 1'b1 & ProcessIdle == 1'b1) begin
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RegData <= 96'd0;
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RegWidth <= 7'd0;
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CheckMode <= 1'b0;
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end else if(RegValid == 1'b0 & (DataInEnable == 1'b1 | DataEnd == 1'b1)) begin
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if(ImageEnable == 1'b1) begin
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if(ImageEnable == 1'b1) begin
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if(RegData[39: 8] == 32'hFF00FF00) begin
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if(RegData[39: 8] == 32'hFF00FF00 & CheckMode != 1'b1) begin
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RegWidth <= RegWidth + 16;
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RegWidth <= RegWidth + 7'd16;
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RegData[95:64] <= {8'h00,RegData[71:48]};
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RegData[95:64] <= {8'h00,RegData[71:48]};
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RegData[63:32] <= {RegData[47:40],16'hFFFF,RegData[7:0]};
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RegData[63:32] <= {RegData[47:40],16'hFFFF,RegData[7:0]};
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end else if(RegData[39:24] == 16'hFF00 &
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CheckMode <= 1'b0;
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RegData[15: 0] == 16'hFF00) begin
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end else if(RegData[39:24] == 16'hFF00 & RegData[15: 0] == 16'hFF00 & CheckMode != 1'b1) begin
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RegWidth <= RegWidth + 16;
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RegWidth <= RegWidth + 7'd16;
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RegData[95:64] <= {8'h00,RegData[71:48]};
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RegData[95:64] <= {8'h00,RegData[71:48]};
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RegData[63:32] <= {RegData[47:40],8'hFF,RegData[23:16],8'hFF};
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RegData[63:32] <= {RegData[47:40],8'hFF,RegData[23:16],8'hFF};
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CheckMode <= 1'b1;
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end else if(RegData[31: 0] == 32'hFF00FF00) begin
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end else if(RegData[31: 0] == 32'hFF00FF00) begin
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RegWidth <= RegWidth + 16;
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RegWidth <= RegWidth + 7'd16;
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RegData[95:64] <= {16'h0000,RegData[71:56]};
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RegData[95:64] <= {16'h0000,RegData[63:48]};
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RegData[63:32] <= {RegData[55:40],16'hFFFF};
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RegData[63:32] <= {RegData[47:32],16'hFFFF};
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end else if(RegData[39:24] == 16'hFF00) begin
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CheckMode <= 1'b1;
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RegWidth <= RegWidth + 24;
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end else if(RegData[39:24] == 16'hFF00 & CheckMode != 1'b1) begin
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RegWidth <= RegWidth + 7'd24;
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RegData[95:64] <= {RegData[71:40]};
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RegData[95:64] <= {RegData[71:40]};
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RegData[63:32] <= {8'hFF,RegData[23:0]};
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RegData[63:32] <= {8'hFF,RegData[23:0]};
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CheckMode <= 1'b0;
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end else if(RegData[31:16] == 16'hFF00) begin
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end else if(RegData[31:16] == 16'hFF00) begin
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RegWidth <= RegWidth + 24;
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RegWidth <= RegWidth + 7'd24;
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RegData[95:64] <= {RegData[71:40]};
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RegData[95:64] <= {RegData[71:40]};
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RegData[63:32] <= {RegData[39:32],8'hFF,RegData[15:0]};
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RegData[63:32] <= {RegData[39:32],8'hFF,RegData[15:0]};
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CheckMode <= 1'b0;
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end else if(RegData[23: 8] == 16'hFF00) begin
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end else if(RegData[23: 8] == 16'hFF00) begin
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RegWidth <= RegWidth + 24;
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RegWidth <= RegWidth + 7'd24;
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RegData[95:64] <= {RegData[71:40]};
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RegData[95:64] <= {RegData[71:40]};
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RegData[63:32] <= {RegData[39:32],RegData[31:24],8'hFF,RegData[7:0]};
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RegData[63:32] <= {RegData[39:32],RegData[31:24],8'hFF,RegData[7:0]};
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CheckMode <= 1'b0;
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end else if(RegData[15: 0] == 16'hFF00) begin
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end else if(RegData[15: 0] == 16'hFF00) begin
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RegWidth <= RegWidth + 24;
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RegWidth <= RegWidth + 7'd24;
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RegData[95:64] <= {RegData[71:40]};
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RegData[95:64] <= {RegData[71:40]};
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RegData[63:32] <= {RegData[39:32],RegData[31:16],8'hFF};
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RegData[63:32] <= {RegData[39:32],RegData[31:16],8'hFF};
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CheckMode <= 1'b1;
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end else begin
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end else begin
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RegWidth <= RegWidth + 32;
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RegWidth <= RegWidth + 7'd32;
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RegData[95:64] <= RegData[63:32];
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RegData[95:64] <= RegData[63:32];
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RegData[63:32] <= RegData[31:0];
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RegData[63:32] <= RegData[31:0];
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CheckMode <= 1'b0;
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end
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end
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end else begin
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end else begin
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RegWidth <= RegWidth + 32;
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RegWidth <= RegWidth + 7'd32;
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RegData[95:64] <= RegData[63:32];
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RegData[95:64] <= RegData[63:32];
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RegData[63:32] <= RegData[31:0];
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RegData[63:32] <= RegData[31:0];
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CheckMode <= 1'b0;
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end
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end
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RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]};
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RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]};
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end else if(UseBit == 1'b1) begin
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end else if(UseBit == 1'b1) begin
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RegWidth <= RegWidth - UseWidth;
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RegWidth <= RegWidth - UseWidth;
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end else if(UseByte == 1'b1) begin
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end else if(UseByte == 1'b1) begin
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RegWidth <= RegWidth - 8;
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RegWidth <= RegWidth - 7'd8;
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end else if(UseWord == 1'b1) begin
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end else if(UseWord == 1'b1) begin
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RegWidth <= RegWidth - 16;
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RegWidth <= RegWidth - 7'd16;
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end
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end
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end
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end
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end
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end
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// PickUp with End of Jpeg Data
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always @(posedge clk or negedge rst) begin
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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if(!rst) begin
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DataEnd <= 1'b0;
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DataEnd <= 1'b0;
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end else begin
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end else begin
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if(ProcessIdle) begin
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if(ProcessIdle) begin
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DataEnd <= 1'b0;
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DataEnd <= 1'b0;
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end else if(ImageEnable == 1'b1 & (RegData[39:24] == 16'hFFD9 | RegData[31:16] == 16'hFFD9 | RegData[23: 8] == 16'hFFD9 | RegData[15: 0] == 16'hFFD9)) begin
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end else if(ImageEnable == 1'b1 & ((RegData[39:24] == 16'hFFD9 & CheckMode != 1'b1) | RegData[31:16] == 16'hFFD9 | RegData[23: 8] == 16'hFFD9 | RegData[15: 0] == 16'hFFD9)) begin
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DataEnd <= 1'b1;
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DataEnd <= 1'b1;
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end
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end
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end
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end
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end
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end
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function [31:0] SliceData;
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function [31:0] SliceData;
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input [95:0] RegData;
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input [95:0] RegData;
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input [7:0] RegWidth;
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input [7:0] RegWidth;
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case(RegWidth)
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case(RegWidth)
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//8'd33: SliceData = RegData[32: 1];
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//8'd34: SliceData = RegData[33: 2];
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//8'd35: SliceData = RegData[34: 3];
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//8'd36: SliceData = RegData[35: 4];
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//8'd37: SliceData = RegData[36: 5];
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//8'd38: SliceData = RegData[37: 6];
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//8'd39: SliceData = RegData[38: 7];
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8'd40: SliceData = RegData[39: 8];
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//8'd41: SliceData = RegData[40: 9];
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//8'd42: SliceData = RegData[41:10];
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//8'd43: SliceData = RegData[42:11];
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//8'd44: SliceData = RegData[43:12];
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//8'd45: SliceData = RegData[44:13];
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//8'd46: SliceData = RegData[45:14];
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//8'd47: SliceData = RegData[46:15];
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8'd48: SliceData = RegData[47:16];
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//8'd49: SliceData = RegData[48:17];
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//8'd50: SliceData = RegData[49:18];
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//8'd51: SliceData = RegData[50:19];
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//8'd52: SliceData = RegData[51:20];
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//8'd53: SliceData = RegData[52:21];
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//8'd54: SliceData = RegData[53:22];
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//8'd55: SliceData = RegData[54:23];
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8'd56: SliceData = RegData[55:24];
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//8'd57: SliceData = RegData[56:25];
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//8'd58: SliceData = RegData[57:26];
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//8'd59: SliceData = RegData[58:27];
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//8'd60: SliceData = RegData[59:28];
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//8'd61: SliceData = RegData[60:29];
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//8'd62: SliceData = RegData[61:30];
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//8'd63: SliceData = RegData[62:31];
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8'd64: SliceData = RegData[63:32];
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8'd65: SliceData = RegData[64:33];
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8'd65: SliceData = RegData[64:33];
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8'd66: SliceData = RegData[65:34];
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8'd66: SliceData = RegData[65:34];
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8'd67: SliceData = RegData[66:35];
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8'd67: SliceData = RegData[66:35];
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8'd68: SliceData = RegData[67:36];
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8'd68: SliceData = RegData[67:36];
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8'd69: SliceData = RegData[68:37];
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8'd69: SliceData = RegData[68:37];
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endcase
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endcase
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endfunction
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endfunction
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reg OutEnable;
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reg OutEnable;
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reg PreEnable;
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reg PreEnable;
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reg [31:0] DataOut;
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reg [31:0] DataOut;
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always @(posedge clk or negedge rst) begin
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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if(!rst) begin
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OutEnable <= 1'b0;
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OutEnable <= 1'b0;
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PreEnable <= 1'b0;
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PreEnable <= 1'b0;
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DataOut <= 32'h00000000;
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DataOut <= 32'h00000000;
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end else begin
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end else begin
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OutEnable <= RegWidth >64;
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if(DataEnd == 1'b1 & ProcessIdle == 1'b1) begin
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OutEnable <= 1'b0;
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PreEnable <= 1'b0;
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DataOut <= 32'h00000000;
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end else begin
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OutEnable <= RegValid;
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PreEnable <= (UseBit == 1'b1 | UseByte == 1'b1 | UseWord == 1'b1);
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PreEnable <= (UseBit == 1'b1 | UseByte == 1'b1 | UseWord == 1'b1);
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DataOut <= SliceData(RegData,RegWidth);
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DataOut <= SliceData(RegData,RegWidth);
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end
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end
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end
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end
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end
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assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0;
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assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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