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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Rev. Date Description
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// Rev. Date Description
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// 1.01 2006/10/01 1st Release
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// 1.01 2006/10/01 1st Release
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// $Id:
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//---------------------------------------------------------------------------
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`timescale 1ps / 1ps
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`timescale 1ps / 1ps
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module jpeg_ycbcr
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module jpeg_ycbcr(
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(
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rst,
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rst,
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clk,
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clk,
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ProcessInit,
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DataInEnable,
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DataInEnable,
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DataInPage,
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DataInPage,
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DataInCount,
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DataInCount,
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DataInIdle,
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DataInIdle,
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Data0In,
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Data0In,
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Line 39... |
);
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);
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input rst;
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input rst;
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input clk;
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input clk;
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input ProcessInit;
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input DataInEnable;
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input DataInEnable;
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input [2:0] DataInPage;
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input [2:0] DataInPage;
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input [1:0] DataInCount;
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input [1:0] DataInCount;
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output DataInIdle;
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output DataInIdle;
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input [8:0] Data0In;
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input [8:0] Data0In;
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output [15:0] OutPixelY;
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output [15:0] OutPixelY;
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output [7:0] OutR;
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output [7:0] OutR;
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output [7:0] OutG;
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output [7:0] OutG;
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output [7:0] OutB;
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output [7:0] OutB;
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reg DataInBank;
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reg [2:0] DataInColor;
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reg [2:0] DataInColor;
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reg [11:0] DataInBlockX;
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reg [11:0] DataInBlockX;
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reg [11:0] DataInBlockY;
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reg [11:0] DataInBlockY;
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reg BankAActive;
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reg BankBActive;
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wire BankAEnable;
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wire BankBEnable;
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wire [8:0] BankAY;
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wire [8:0] BankACb;
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wire [8:0] BankACr;
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wire [8:0] BankBY;
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wire [8:0] BankBCb;
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wire [8:0] BankBCr;
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reg [11:0] BankABlockX;
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reg [11:0] BankABlockY;
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reg [11:0] BankBBlockX;
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reg [11:0] BankBBlockY;
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wire ConvertEnable;
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wire ConvertEnable;
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wire ConvertRead;
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wire ConvertBank;
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wire ConvertBank;
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wire [7:0] ConvertAddress;
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wire [7:0] ConvertAddress;
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wire [8:0] DataY;
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wire [8:0] DataY;
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wire [8:0] DataCb;
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wire [8:0] DataCb;
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wire [8:0] DataCr;
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wire [8:0] DataCr;
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wire [11:0] ConvertBlockX;
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wire [11:0] ConvertBlockX;
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wire [11:0] ConvertBlockY;
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wire [11:0] ConvertBlockY;
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wire BankAIdle;
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wire BankBIdle;
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always @(posedge clk or negedge rst) begin
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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if(!rst) begin
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DataInBank <= 1'b0;
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DataInColor <= 3'b000;
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DataInColor <= 3'b000;
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DataInBlockX <= 12'h000;
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end else begin
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DataInBlockY <= 12'h000;
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if(ProcessInit) begin
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BankAActive <= 1'b0;
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DataInColor <= 3'b000;
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BankBActive <= 1'b0;
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end else if(DataInEnable == 1'b1 & DataInPage == 3'b111 & DataInCount == 2'b11) begin
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BankABlockX <= 12'h000;
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BankABlockY <= 12'h000;
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BankBBlockX <= 12'h000;
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BankBBlockY <= 12'h000;
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end else begin // if (!rst)
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if(DataInEnable == 1'b1 & DataInColor == 3'b101 &
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DataInPage == 3'b111 & DataInCount == 2'b11) begin
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end
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if(DataInEnable == 1'b1 & DataInColor == 3'b101 &
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DataInPage == 3'b111 & DataInCount == 2'b11 &
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DataInBank == 1'b0 & BankAActive == 1'b0) begin
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BankAActive <= 1'b1;
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BankABlockX <= DataInBlockX;
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BankABlockY <= DataInBlockY;
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end else if(ConvertBank == 1'b0 & ConvertAddress == 7'b111) begin
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BankAActive <= 1'b0;
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end
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if(DataInEnable == 1'b1 & DataInColor == 3'b101 &
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DataInPage == 3'b111 & DataInCount == 2'b11 &
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DataInBank == 1'b1 & BankBActive == 1'b0) begin
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BankBActive <= 1'b1;
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BankBBlockX <= DataInBlockX;
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BankBBlockY <= DataInBlockY;
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end else if(ConvertBank == 1'b1 & ConvertAddress == 7'b111) begin
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BankBActive <= 1'b0;
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end
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if(DataInEnable == 1'b1 &
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DataInPage == 3'b111 & DataInCount == 2'b11) begin
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if(DataInColor == 3'b101) begin
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if(DataInColor == 3'b101) begin
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DataInColor <= 3'b000;
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DataInColor <= 3'b000;
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DataInBank <= ~DataInBank;
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if(DataInBlockWidth == DataInBlockX +1) begin
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DataInBlockX <= 12'h000;
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DataInBlockY <= DataInBlockY + 12'h001;
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end else begin
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DataInBlockX <= DataInBlockX + 12'h001;
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end
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end else begin
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end else begin
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DataInColor <= DataInColor + 3'b001;
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DataInColor <= DataInColor + 3'b001;
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end // else: !if(DataInColor == 3'b101)
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end
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end // if (DataInEnable == 1'b1 &...
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end
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end // else: !if(!rst)
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end // always @ (posedge clk or negedge rst)
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assign BankAEnable = DataInEnable == 1'b1 & DataInBank == 1'b0;
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assign BankBEnable = DataInEnable == 1'b1 & DataInBank == 1'b1;
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/*
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assign ConvertBlockX = (ConvertBank)?BankBBlockX:BankABlockX;
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assign ConvertBlockY = (ConvertBank)?BankBBlockY:BankABlockY;
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*/
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assign ConvertEnable = DataInEnable == 1'b1 & DataInColor == 3'b101 &
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DataInPage == 3'b111 & DataInCount == 2'b11;
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assign DataInIdle = BankAActive == 1'b0 | BankBActive == 1'b0;
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end
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end
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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// YCbCr Memory
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// YCbCr Memory
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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jpeg_ycbcr_mem u_jpeg_ycbcr_mem0(
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jpeg_ycbcr_mem u_jpeg_ycbcr_mem(
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.rst ( rst ),
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.clk(clk),
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.clk(clk),
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.DataInEnable (BankAEnable),
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.DataInit ( ProcessInit ),
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.DataInColor (DataInColor),
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.DataInPage (DataInPage),
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.DataInCount (DataInCount),
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.Data0In (Data0In),
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.Data1In (Data1In),
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.DataOutAddress (ConvertAddress),
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.DataOutY (BankAY),
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.DataOutCb (BankACb),
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.DataOutCr (BankACr)
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);
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jpeg_ycbcr_mem u_jpeg_ycbcr_mem1(
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.clk(clk),
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.DataInEnable (BankBEnable),
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.DataInEnable ( DataInEnable ),
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.DataInColor (DataInColor),
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.DataInColor (DataInColor),
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.DataInPage (DataInPage),
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.DataInPage (DataInPage),
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.DataInCount (DataInCount),
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.DataInCount (DataInCount),
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.Data0In (Data0In),
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.Data0In (Data0In),
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.Data1In (Data1In),
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.Data1In (Data1In),
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.DataOutEnable ( ConvertEnable ),
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.DataOutAddress (ConvertAddress),
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.DataOutAddress (ConvertAddress),
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.DataOutY (BankBY),
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.DataOutRead ( ConvertRead ),
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.DataOutCb (BankBCb),
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.DataOutY ( DataY ),
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.DataOutCr (BankBCr)
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.DataOutCb ( DataCb ),
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.DataOutCr ( DataCr )
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);
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);
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reg ConvertBankD;
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always @(posedge clk or negedge rst) begin
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if(!rst) ConvertBankD <= 1'b0;
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else ConvertBankD <= ConvertBank;
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end
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assign DataY = (ConvertBankD)?BankBY :BankAY;
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assign DataCb = (ConvertBankD)?BankBCb:BankACb;
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assign DataCr = (ConvertBankD)?BankBCr:BankACr;
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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// YCbCr to RGB
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// YCbCr to RGB
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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jpeg_ycbcbr2rgb u_jpeg_ycbcr2rgb(
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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DataInBlockX <= 12'h000;
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DataInBlockY <= 12'h000;
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end else begin
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if(ProcessInit) begin
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DataInBlockX <= 12'h000;
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DataInBlockY <= 12'h000;
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end else if((ConvertRead == 1'b1) && (ConvertAddress == 5'h1F)) begin
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if(DataInBlockWidth == DataInBlockX +1) begin
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DataInBlockX <= 12'h000;
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DataInBlockY <= DataInBlockY + 12'h001;
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end else begin
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DataInBlockX <= DataInBlockX + 12'h001;
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end
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end
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end
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end
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jpeg_ycbcr2rgb u_jpeg_yccr2rgb(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.InEnable ( ConvertEnable ),
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.InEnable ( ConvertEnable ),
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.InRead ( ConvertRead ),
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.InBlockX ( DataInBlockX ),
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.InBlockX ( DataInBlockX ),
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.InBlockY ( DataInBlockY ),
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.InBlockY ( DataInBlockY ),
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.InIdle ( ConvertIdle ),
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.InBank ( ConvertBank ),
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.InAddress ( ConvertAddress ),
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.InAddress ( ConvertAddress ),
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.InY ( DataY ),
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.InY ( DataY ),
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.InCb ( DataCb ),
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.InCb ( DataCb ),
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.InCr ( DataCr ),
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.InCr ( DataCr ),
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| Line 223... |
Line 152... |
.OutPixelY ( OutPixelY ),
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.OutPixelY ( OutPixelY ),
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.OutR ( OutR ),
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.OutR ( OutR ),
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.OutG ( OutG ),
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.OutG ( OutG ),
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.OutB ( OutB )
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.OutB ( OutB )
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);
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);
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endmodule // jpeg_ycbcr
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endmodule
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No newline at end of file
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No newline at end of file
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