Line 12... |
Line 12... |
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
// Rev. Date Description
|
// Rev. Date Description
|
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
// 1.01 2006/10/01 1st Release
|
// 1.01 2006/10/01 1st Release
|
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
// $Id:
|
|
//---------------------------------------------------------------------------
|
|
`timescale 1ps / 1ps
|
`timescale 1ps / 1ps
|
|
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// JPEG YCbCr -> RGB Conveter
|
// JPEG YCbCr -> RGB Conveter
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
module jpeg_ycbcbr2rgb
|
module jpeg_ycbcr2rgb(
|
(
|
|
rst,
|
rst,
|
clk,
|
clk,
|
|
|
InEnable,
|
InEnable,
|
|
InRead,
|
InBlockX,
|
InBlockX,
|
InBlockY,
|
InBlockY,
|
InIdle,
|
|
InBank,
|
|
InAddress,
|
InAddress,
|
InY,
|
InY,
|
InCb,
|
InCb,
|
InCr,
|
InCr,
|
|
|
Line 46... |
Line 42... |
|
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
|
|
input InEnable;
|
input InEnable;
|
|
output InRead;
|
input [11:0] InBlockX;
|
input [11:0] InBlockX;
|
input [11:0] InBlockY;
|
input [11:0] InBlockY;
|
output InIdle;
|
|
output InBank;
|
|
output [7:0] InAddress;
|
output [7:0] InAddress;
|
input [8:0] InY;
|
input [8:0] InY;
|
input [8:0] InCb;
|
input [8:0] InCb;
|
input [8:0] InCr;
|
input [8:0] InCr;
|
|
|
Line 66... |
Line 61... |
|
|
reg RunActive;
|
reg RunActive;
|
reg [7:0] RunCount;
|
reg [7:0] RunCount;
|
reg [11:0] RunBlockX;
|
reg [11:0] RunBlockX;
|
reg [11:0] RunBlockY;
|
reg [11:0] RunBlockY;
|
reg RunBank;
|
|
|
|
always @(posedge clk or negedge rst) begin
|
always @(posedge clk or negedge rst) begin
|
if(!rst) begin
|
if(!rst) begin
|
RunActive <= 1'b0;
|
RunActive <= 1'b0;
|
RunBank <= 1'b0;
|
|
RunCount <= 8'h00;
|
RunCount <= 8'h00;
|
RunBlockX <= 12'h000;
|
RunBlockX <= 12'h000;
|
RunBlockY <= 12'h000;
|
RunBlockY <= 12'h000;
|
end else begin
|
end else begin
|
if(RunActive == 1'b0) begin
|
if(RunActive == 1'b0) begin
|
Line 86... |
Line 79... |
end
|
end
|
RunCount <= 8'h00;
|
RunCount <= 8'h00;
|
end else begin
|
end else begin
|
if(RunCount == 8'hFF) begin
|
if(RunCount == 8'hFF) begin
|
RunActive <= 1'b0;
|
RunActive <= 1'b0;
|
RunBank <= ~RunBank;
|
|
RunCount <= 8'h00;
|
RunCount <= 8'h00;
|
end else begin
|
end else begin
|
RunCount <= RunCount +1;
|
RunCount <= RunCount +8'd1;
|
|
end
|
|
end
|
|
end
|
end
|
end
|
end // else: !if(RunActive == 1'b0)
|
|
end // else: !if(!rst)
|
|
end // always @ (posedge clk or negedge rst)
|
|
|
|
assign InIdle = RunActive == 1'b0 | (RunActive == 1'b1 & RunCount == 8'hFF);
|
assign InRead = RunActive;
|
assign InAddress = RunCount;
|
assign InAddress = RunCount;
|
assign InBank = RunBank;
|
|
|
|
reg PreEnable;
|
reg PreEnable;
|
reg [15:0] PreCountX;
|
reg [15:0] PreCountX;
|
reg [15:0] PreCountY;
|
reg [15:0] PreCountY;
|
reg Phase0Enable;
|
reg Phase0Enable;
|
Line 147... |
Line 138... |
assign DataCb = InCb;
|
assign DataCb = InCb;
|
assign DataCr = InCr;
|
assign DataCr = InCr;
|
|
|
reg signed [8:0] Phase1Y,Phase1Cb,Phase1Cr;
|
reg signed [8:0] Phase1Y,Phase1Cb,Phase1Cr;
|
reg signed [8:0] Phase2Y,Phase2Cb,Phase2Cr;
|
reg signed [8:0] Phase2Y,Phase2Cb,Phase2Cr;
|
reg signed [8:0] Phase3Y,Phase3Cb,Phase3Cr;
|
|
|
|
always @(posedge clk or negedge rst) begin
|
always @(posedge clk or negedge rst) begin
|
if(!rst) begin
|
if(!rst) begin
|
rgb00r <= 0;
|
rgb00r <= 0;
|
r00r <= 0;
|
r00r <= 0;
|
Line 178... |
Line 168... |
Phase2CountX <= 16'h0000;
|
Phase2CountX <= 16'h0000;
|
Phase2CountY <= 16'h0000;
|
Phase2CountY <= 16'h0000;
|
Phase3Enable <= 1'b0;
|
Phase3Enable <= 1'b0;
|
Phase3CountX <= 16'h0000;
|
Phase3CountX <= 16'h0000;
|
Phase3CountY <= 16'h0000;
|
Phase3CountY <= 16'h0000;
|
end else begin // if (!rst)
|
end else begin
|
// Pre
|
// Pre
|
PreEnable <= RunActive;
|
PreEnable <= RunActive;
|
PreCountX <= {RunBlockX,RunCount[3:0]};
|
PreCountX <= {RunBlockX,RunCount[3:0]};
|
PreCountY <= {RunBlockY,RunCount[7:4]};
|
PreCountY <= {RunBlockY,RunCount[7:4]};
|
|
|
// Phase0
|
// Phase0
|
Phase0Enable <= PreEnable;
|
Phase0Enable <= PreEnable;
|
Phase0CountX <= PreCountX;
|
Phase0CountX <= PreCountX;
|
Phase0CountY <= PreCountY;
|
Phase0CountY <= PreCountY;
|
Phase0Y <= DataY;
|
Phase0Y <= DataY;
|
Phase0Cb <= DataCb;
|
Phase0Cb <= DataCb;
|
Phase0Cr <= DataCr;
|
Phase0Cr <= DataCr;
|
|
|
// Phase1
|
// Phase1
|
Phase1Enable <= Phase0Enable;
|
Phase1Enable <= Phase0Enable;
|
Phase1CountX <= Phase0CountX;
|
Phase1CountX <= Phase0CountX;
|
Phase1CountY <= Phase0CountY;
|
Phase1CountY <= Phase0CountY;
|
|
|
rgb00r <= 32'h02000000 + {Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8:0],18'h0000};
|
rgb00r <= 32'h02000000 + {Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8:0],18'h0000};
|
r00r <= Phase0Cr * C_RR;
|
r00r <= Phase0Cr * C_RR;
|
g00r <= Phase0Cb * C_GB;
|
g00r <= Phase0Cb * C_GB;
|
g01r <= Phase0Cr * C_GR;
|
g01r <= Phase0Cr * C_GR;
|
b00r <= Phase0Cb * C_BB;
|
b00r <= Phase0Cb * C_BB;
|
|
|
Phase1Y <= Phase0Y;
|
Phase1Y <= Phase0Y;
|
Phase1Cb <= Phase0Cb;
|
Phase1Cb <= Phase0Cb;
|
Phase1Cr <= Phase0Cr;
|
Phase1Cr <= Phase0Cr;
|
|
|
|
|
// Phase2
|
// Phase2
|
Phase2Enable <= Phase1Enable;
|
Phase2Enable <= Phase1Enable;
|
Phase2CountX <= Phase1CountX;
|
Phase2CountX <= Phase1CountX;
|
Phase2CountY <= Phase1CountY;
|
Phase2CountY <= Phase1CountY;
|
|
|
r10r <= rgb00r + r00r;
|
r10r <= rgb00r + r00r;
|
g10r <= rgb00r - g00r;
|
g10r <= rgb00r - g00r;
|
g11r <= g01r;
|
g11r <= g01r;
|
b10r <= rgb00r + b00r;
|
b10r <= rgb00r + b00r;
|
|
|
Line 225... |
Line 218... |
Phase3CountX <= Phase2CountX;
|
Phase3CountX <= Phase2CountX;
|
Phase3CountY <= Phase2CountY;
|
Phase3CountY <= Phase2CountY;
|
r20r <= r10r;
|
r20r <= r10r;
|
g20r <= g10r - g11r;
|
g20r <= g10r - g11r;
|
b20r <= b10r;
|
b20r <= b10r;
|
|
end
|
Phase3Y <= Phase2Y;
|
end
|
Phase3Cb <= Phase2Cb;
|
|
Phase3Cr <= Phase2Cr;
|
|
|
|
end // else: !if(!rst)
|
|
end // always @ (posedge clk or negedge rst)
|
|
|
|
assign OutEnable = Phase3Enable;
|
assign OutEnable = Phase3Enable;
|
assign OutPixelX = Phase3CountX;
|
assign OutPixelX = Phase3CountX;
|
assign OutPixelY = Phase3CountY;
|
assign OutPixelY = Phase3CountY;
|
assign OutR = (r20r[31])?8'h00:(r20r[26])?8'hFF:r20r[25:18];
|
assign OutR = (r20r[31])?8'h00:(r20r[26])?8'hFF:r20r[25:18];
|
assign OutG = (g20r[31])?8'h00:(g20r[26])?8'hFF:g20r[25:18];
|
assign OutG = (g20r[31])?8'h00:(g20r[26])?8'hFF:g20r[25:18];
|
assign OutB = (b20r[31])?8'h00:(b20r[26])?8'hFF:b20r[25:18];
|
assign OutB = (b20r[31])?8'h00:(b20r[26])?8'hFF:b20r[25:18];
|
|
endmodule
|
endmodule // jpeg_ycbcbr2rgb
|
|
|
|
No newline at end of file
|
No newline at end of file
|