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Line 12... |
//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Rev. Date Description
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// Rev. Date Description
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// 1.01 2006/10/01 1st Release
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// 1.01 2006/10/01 1st Release
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// $Id:
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//---------------------------------------------------------------------------
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`timescale 1ps / 1ps
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`timescale 1ps / 1ps
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// JPEG YCbCr -> RGB Conveter
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// JPEG YCbCr -> RGB Conveter
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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module jpeg_ycbcbr2rgb
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module jpeg_ycbcr2rgb(
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(
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rst,
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rst,
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clk,
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clk,
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InEnable,
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InEnable,
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InRead,
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InBlockX,
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InBlockX,
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InBlockY,
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InBlockY,
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InIdle,
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InBank,
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InAddress,
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InAddress,
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InY,
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InY,
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InCb,
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InCb,
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InCr,
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InCr,
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| Line 46... |
Line 42... |
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input clk;
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input clk;
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input rst;
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input rst;
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input InEnable;
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input InEnable;
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output InRead;
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input [11:0] InBlockX;
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input [11:0] InBlockX;
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input [11:0] InBlockY;
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input [11:0] InBlockY;
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output InIdle;
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output InBank;
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output [7:0] InAddress;
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output [7:0] InAddress;
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input [8:0] InY;
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input [8:0] InY;
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input [8:0] InCb;
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input [8:0] InCb;
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input [8:0] InCr;
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input [8:0] InCr;
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| Line 66... |
Line 61... |
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reg RunActive;
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reg RunActive;
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reg [7:0] RunCount;
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reg [7:0] RunCount;
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reg [11:0] RunBlockX;
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reg [11:0] RunBlockX;
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reg [11:0] RunBlockY;
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reg [11:0] RunBlockY;
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reg RunBank;
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always @(posedge clk or negedge rst) begin
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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if(!rst) begin
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RunActive <= 1'b0;
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RunActive <= 1'b0;
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RunBank <= 1'b0;
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RunCount <= 8'h00;
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RunCount <= 8'h00;
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RunBlockX <= 12'h000;
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RunBlockX <= 12'h000;
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RunBlockY <= 12'h000;
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RunBlockY <= 12'h000;
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end else begin
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end else begin
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if(RunActive == 1'b0) begin
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if(RunActive == 1'b0) begin
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| Line 86... |
Line 79... |
end
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end
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RunCount <= 8'h00;
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RunCount <= 8'h00;
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end else begin
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end else begin
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if(RunCount == 8'hFF) begin
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if(RunCount == 8'hFF) begin
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RunActive <= 1'b0;
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RunActive <= 1'b0;
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RunBank <= ~RunBank;
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RunCount <= 8'h00;
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RunCount <= 8'h00;
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end else begin
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end else begin
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RunCount <= RunCount +1;
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RunCount <= RunCount +8'd1;
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end
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end
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end
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end
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end
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end // else: !if(RunActive == 1'b0)
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end // else: !if(!rst)
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end // always @ (posedge clk or negedge rst)
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assign InIdle = RunActive == 1'b0 | (RunActive == 1'b1 & RunCount == 8'hFF);
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assign InRead = RunActive;
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assign InAddress = RunCount;
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assign InAddress = RunCount;
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assign InBank = RunBank;
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reg PreEnable;
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reg PreEnable;
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reg [15:0] PreCountX;
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reg [15:0] PreCountX;
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reg [15:0] PreCountY;
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reg [15:0] PreCountY;
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reg Phase0Enable;
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reg Phase0Enable;
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| Line 147... |
Line 138... |
assign DataCb = InCb;
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assign DataCb = InCb;
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assign DataCr = InCr;
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assign DataCr = InCr;
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reg signed [8:0] Phase1Y,Phase1Cb,Phase1Cr;
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reg signed [8:0] Phase1Y,Phase1Cb,Phase1Cr;
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reg signed [8:0] Phase2Y,Phase2Cb,Phase2Cr;
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reg signed [8:0] Phase2Y,Phase2Cb,Phase2Cr;
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reg signed [8:0] Phase3Y,Phase3Cb,Phase3Cr;
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always @(posedge clk or negedge rst) begin
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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if(!rst) begin
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rgb00r <= 0;
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rgb00r <= 0;
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r00r <= 0;
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r00r <= 0;
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Line 168... |
Phase2CountX <= 16'h0000;
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Phase2CountX <= 16'h0000;
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Phase2CountY <= 16'h0000;
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Phase2CountY <= 16'h0000;
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Phase3Enable <= 1'b0;
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Phase3Enable <= 1'b0;
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Phase3CountX <= 16'h0000;
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Phase3CountX <= 16'h0000;
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Phase3CountY <= 16'h0000;
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Phase3CountY <= 16'h0000;
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end else begin // if (!rst)
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end else begin
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// Pre
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// Pre
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PreEnable <= RunActive;
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PreEnable <= RunActive;
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PreCountX <= {RunBlockX,RunCount[3:0]};
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PreCountX <= {RunBlockX,RunCount[3:0]};
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PreCountY <= {RunBlockY,RunCount[7:4]};
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PreCountY <= {RunBlockY,RunCount[7:4]};
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// Phase0
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// Phase0
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Phase0Enable <= PreEnable;
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Phase0Enable <= PreEnable;
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Phase0CountX <= PreCountX;
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Phase0CountX <= PreCountX;
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Phase0CountY <= PreCountY;
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Phase0CountY <= PreCountY;
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Phase0Y <= DataY;
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Phase0Y <= DataY;
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Phase0Cb <= DataCb;
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Phase0Cb <= DataCb;
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Phase0Cr <= DataCr;
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Phase0Cr <= DataCr;
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// Phase1
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// Phase1
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Phase1Enable <= Phase0Enable;
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Phase1Enable <= Phase0Enable;
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Phase1CountX <= Phase0CountX;
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Phase1CountX <= Phase0CountX;
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Phase1CountY <= Phase0CountY;
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Phase1CountY <= Phase0CountY;
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rgb00r <= 32'h02000000 + {Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8:0],18'h0000};
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rgb00r <= 32'h02000000 + {Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8:0],18'h0000};
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r00r <= Phase0Cr * C_RR;
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r00r <= Phase0Cr * C_RR;
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g00r <= Phase0Cb * C_GB;
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g00r <= Phase0Cb * C_GB;
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g01r <= Phase0Cr * C_GR;
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g01r <= Phase0Cr * C_GR;
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b00r <= Phase0Cb * C_BB;
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b00r <= Phase0Cb * C_BB;
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Phase1Y <= Phase0Y;
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Phase1Y <= Phase0Y;
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Phase1Cb <= Phase0Cb;
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Phase1Cb <= Phase0Cb;
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Phase1Cr <= Phase0Cr;
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Phase1Cr <= Phase0Cr;
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// Phase2
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// Phase2
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Phase2Enable <= Phase1Enable;
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Phase2Enable <= Phase1Enable;
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Phase2CountX <= Phase1CountX;
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Phase2CountX <= Phase1CountX;
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Phase2CountY <= Phase1CountY;
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Phase2CountY <= Phase1CountY;
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r10r <= rgb00r + r00r;
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r10r <= rgb00r + r00r;
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g10r <= rgb00r - g00r;
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g10r <= rgb00r - g00r;
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g11r <= g01r;
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g11r <= g01r;
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b10r <= rgb00r + b00r;
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b10r <= rgb00r + b00r;
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Line 218... |
Phase3CountX <= Phase2CountX;
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Phase3CountX <= Phase2CountX;
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Phase3CountY <= Phase2CountY;
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Phase3CountY <= Phase2CountY;
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r20r <= r10r;
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r20r <= r10r;
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g20r <= g10r - g11r;
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g20r <= g10r - g11r;
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b20r <= b10r;
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b20r <= b10r;
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end
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Phase3Y <= Phase2Y;
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end
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Phase3Cb <= Phase2Cb;
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Phase3Cr <= Phase2Cr;
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end // else: !if(!rst)
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end // always @ (posedge clk or negedge rst)
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assign OutEnable = Phase3Enable;
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assign OutEnable = Phase3Enable;
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assign OutPixelX = Phase3CountX;
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assign OutPixelX = Phase3CountX;
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assign OutPixelY = Phase3CountY;
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assign OutPixelY = Phase3CountY;
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assign OutR = (r20r[31])?8'h00:(r20r[26])?8'hFF:r20r[25:18];
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assign OutR = (r20r[31])?8'h00:(r20r[26])?8'hFF:r20r[25:18];
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assign OutG = (g20r[31])?8'h00:(g20r[26])?8'hFF:g20r[25:18];
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assign OutG = (g20r[31])?8'h00:(g20r[26])?8'hFF:g20r[25:18];
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assign OutB = (b20r[31])?8'h00:(b20r[26])?8'hFF:b20r[25:18];
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assign OutB = (b20r[31])?8'h00:(b20r[26])?8'hFF:b20r[25:18];
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endmodule
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endmodule // jpeg_ycbcbr2rgb
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No newline at end of file
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No newline at end of file
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