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// Belong to :
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// Belong to :
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// Author : H.Ishihara
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// Author : H.Ishihara
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// E-Mail : hidemi@sweetcafe.jp
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// E-Mail : hidemi@sweetcafe.jp
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// HomePage : http://www.sweetcafe.jp/
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// HomePage : http://www.sweetcafe.jp/
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// Date : 2006/10/01
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// Date : 2006/10/01
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// Rev. : 1.1
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// Rev. : 2.00
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Rev. Date Description
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// Rev. Date Description
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// 1.01 2006/10/01 1st Release
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// 1.01 2006/10/01 1st Release
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// 1.02 2006/10/04 remove a WriteData,WriteDataA,WriteDataB wires.
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// 1.02 2006/10/04 remove a WriteData,WriteDataA,WriteDataB wires.
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//---------------------------------------------------------------------------
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// 2.00 2007/03/25 Replace to RAM from D-FF
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// $Id:
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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`timescale 1ps / 1ps
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`timescale 1ps / 1ps
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module jpeg_ycbcr_mem
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module jpeg_ycbcr_mem(
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(
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rst,
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clk,
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clk,
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DataInit,
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DataInEnable,
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DataInEnable,
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DataInColor,
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DataInColor,
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DataInPage,
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DataInPage,
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DataInCount,
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DataInCount,
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Data0In,
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Data0In,
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Data1In,
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Data1In,
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DataOutEnable,
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DataOutAddress,
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DataOutAddress,
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DataOutRead,
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DataOutY,
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DataOutY,
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DataOutCb,
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DataOutCb,
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DataOutCr
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DataOutCr
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);
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);
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input rst;
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input clk;
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input clk;
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input DataInit;
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input DataInEnable;
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input DataInEnable;
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input [2:0] DataInColor;
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input [2:0] DataInColor;
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input [2:0] DataInPage;
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input [2:0] DataInPage;
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input [1:0] DataInCount;
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input [1:0] DataInCount;
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input [8:0] Data0In;
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input [8:0] Data0In;
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input [8:0] Data1In;
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input [8:0] Data1In;
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output DataOutEnable;
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input [7:0] DataOutAddress;
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input [7:0] DataOutAddress;
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input DataOutRead;
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output [8:0] DataOutY;
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output [8:0] DataOutY;
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output [8:0] DataOutCb;
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output [8:0] DataOutCb;
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output [8:0] DataOutCr;
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output [8:0] DataOutCr;
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reg [8:0] MemYA [0:127];
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reg [8:0] MemYA [0:511];
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reg [8:0] MemYB [0:127];
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reg [8:0] MemYB [0:511];
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reg [8:0] MemCbA [0:31];
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reg [8:0] MemCbA [0:127];
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reg [8:0] MemCbB [0:31];
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reg [8:0] MemCbB [0:127];
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reg [8:0] MemCrA [0:31];
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reg [8:0] MemCrA [0:127];
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reg [8:0] MemCrB [0:31];
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reg [8:0] MemCrB [0:127];
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reg [6:0] WriteAddressA;
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reg [1:0] WriteBank, ReadBank;
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reg [6:0] WriteAddressB;
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wire [5:0] DataInAddress;
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always @(DataInColor or DataInPage or DataInCount) begin
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WriteAddressA[6] <= DataInColor[1];
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assign DataInAddress = {DataInPage, DataInCount};
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WriteAddressB[6] <= DataInColor[1];
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// Bank
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always @(posedge clk or negedge rst) begin
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if(!rst) begin
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WriteBank <= 2'd0;
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ReadBank <= 2'd0;
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end else begin
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if(DataInit) begin
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WriteBank <= 2'd0;
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end else if(DataInEnable && (DataInAddress == 5'h1F) && (DataInColor == 3'b101)) begin
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WriteBank <= WriteBank + 2'd1;
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end
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if(DataInit) begin
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ReadBank <= 2'd0;
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end else if(DataOutRead && (DataOutAddress == 8'hFF)) begin
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ReadBank <= ReadBank + 2'd1;
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end
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end
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end
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wire [6:0] WriteAddressA;
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wire [6:0] WriteAddressB;
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function [6:0] F_WriteAddressA;
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input [2:0] DataInColor;
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input [2:0] DataInPage;
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input [1:0] DataInCount;
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begin
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F_WriteAddressA[6] = DataInColor[1];
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if(DataInColor[2] == 1'b0) begin
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if(DataInColor[2] == 1'b0) begin
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if(DataInColor[0] == 1'b0) begin
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F_WriteAddressA[5:4] = DataInCount[1:0];
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case(DataInCount)
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F_WriteAddressA[3] = DataInColor[0] & ~DataInColor[2];
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2'h0: begin
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end else begin
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WriteAddressA[5:0] <= DataInPage + 0;
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F_WriteAddressA[5] = 1'b0;
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WriteAddressB[5:0] <= DataInPage +112 -64;
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F_WriteAddressA[4:3] = DataInCount[1:0];
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end
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end
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2'h1: begin
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F_WriteAddressA[2:0] = DataInPage[2:0];
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WriteAddressA[5:0] <= DataInPage + 16;
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end
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WriteAddressB[5:0] <= DataInPage + 96 -64;
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endfunction
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end
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2'h2: begin
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function [6:0] F_WriteAddressB;
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WriteAddressA[5:0] <= DataInPage + 32;
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input [2:0] DataInColor;
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WriteAddressB[5:0] <= DataInPage + 80 -64;
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input [2:0] DataInPage;
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end
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input [1:0] DataInCount;
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2'h3: begin
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begin
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WriteAddressA[5:0] <= DataInPage + 48;
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F_WriteAddressB[6] = DataInColor[1];
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WriteAddressB[5:0] <= DataInPage + 64 -64;
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if(DataInColor[2] == 1'b0) begin
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end
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F_WriteAddressB[5:4] = ~DataInCount[1:0];
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endcase // case(DataInCount)
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F_WriteAddressB[3] = DataInColor[0] & ~DataInColor[2];
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end else begin // if (DataInColor[0] == 1'b0)
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end else begin
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case(DataInCount)
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F_WriteAddressB[5] = 1'b0;
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2'h0: begin
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F_WriteAddressB[4:3] = ~DataInCount[1:0];
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WriteAddressA[5:0] <= DataInPage + 0 +8;
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end
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WriteAddressB[5:0] <= DataInPage +112 +8 -64;
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F_WriteAddressB[2:0] = DataInPage[2:0];
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end
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end
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2'h1: begin
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endfunction
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WriteAddressA[5:0] <= DataInPage + 16 +8;
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WriteAddressB[5:0] <= DataInPage + 96 +8 -64;
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assign WriteAddressA = F_WriteAddressA(DataInColor, DataInPage, DataInCount);
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end
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assign WriteAddressB = F_WriteAddressB(DataInColor, DataInPage, DataInCount);
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2'h2: begin
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WriteAddressA[5:0] <= DataInPage + 32 +8;
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WriteAddressB[5:0] <= DataInPage + 80 +8 -64;
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end
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2'h3: begin
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WriteAddressA[5:0] <= DataInPage + 48 +8;
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WriteAddressB[5:0] <= DataInPage + 64 +8 -64;
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end
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endcase // case(DataInCount)
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end // else: !if(DataInColor[0] == 1'b0)
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end else begin // if (DataInColor[2] == 1'b0)
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case(DataInCount)
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2'h0: begin
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WriteAddressA[5:0] <= DataInPage + 0;
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WriteAddressB[5:0] <= DataInPage + 56 -32;
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end
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2'h1: begin
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WriteAddressA[5:0] <= DataInPage + 8;
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WriteAddressB[5:0] <= DataInPage + 48 -32;
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end
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2'h2: begin
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WriteAddressA[5:0] <= DataInPage + 16;
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WriteAddressB[5:0] <= DataInPage + 40 -32;
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end
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2'h3: begin
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WriteAddressA[5:0] <= DataInPage + 24;
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WriteAddressB[5:0] <= DataInPage + 32 -32;
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end
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endcase // case(DataInCount)
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end // else: !if(DataInColor[2] == 1'b0)
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end // always @ (DataInColor or DataInPage or DataInCount)
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(DataInColor[2] == 1'b0 & DataInEnable == 1'b1) begin
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if(DataInColor[2] == 1'b0 & DataInEnable == 1'b1) begin
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MemYA[WriteAddressA] <= Data0In;
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MemYA[{WriteBank, WriteAddressA}] <= Data0In;
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MemYB[WriteAddressB] <= Data1In;
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MemYB[{WriteBank, WriteAddressB}] <= Data1In;
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end
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end
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(DataInColor == 3'b100 & DataInEnable == 1'b1) begin
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if(DataInColor == 3'b100 & DataInEnable == 1'b1) begin
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MemCbA[WriteAddressA[4:0]] <= Data0In;
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MemCbA[{WriteBank, WriteAddressA[4:0]}] <= Data0In;
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MemCbB[WriteAddressB[4:0]] <= Data1In;
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MemCbB[{WriteBank, WriteAddressB[4:0]}] <= Data1In;
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end
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end
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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if(DataInColor == 3'b101 & DataInEnable == 1'b1) begin
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if(DataInColor == 3'b101 & DataInEnable == 1'b1) begin
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MemCrA[WriteAddressA[4:0]] <= Data0In;
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MemCrA[{WriteBank, WriteAddressA[4:0]}] <= Data0In;
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MemCrB[WriteAddressB[4:0]] <= Data1In;
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MemCrB[{WriteBank, WriteAddressB[4:0]}] <= Data1In;
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end
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end
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end
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end
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reg [8:0] ReadYA;
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reg [8:0] ReadYA;
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reg [8:0] ReadYB;
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reg [8:0] ReadYB;
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reg [7:0] RegAdrs;
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reg [7:0] RegAdrs;
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always @(posedge clk) begin
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always @(posedge clk) begin
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RegAdrs <= DataOutAddress;
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RegAdrs <= DataOutAddress;
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ReadYA <= MemYA[{DataOutAddress[7],DataOutAddress[5:0]}];
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ReadYA <= MemYA[{ReadBank, DataOutAddress[7],DataOutAddress[5:0]}];
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ReadYB <= MemYB[{DataOutAddress[7],DataOutAddress[5:0]}];
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ReadYB <= MemYB[{ReadBank, DataOutAddress[7],DataOutAddress[5:0]}];
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ReadCbA <= MemCbA[{DataOutAddress[6:5],DataOutAddress[3:1]}];
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ReadCbA <= MemCbA[{ReadBank, DataOutAddress[6:5],DataOutAddress[3:1]}];
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ReadCrA <= MemCrA[{DataOutAddress[6:5],DataOutAddress[3:1]}];
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ReadCrA <= MemCrA[{ReadBank, DataOutAddress[6:5],DataOutAddress[3:1]}];
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ReadCbB <= MemCbB[{DataOutAddress[6:5],DataOutAddress[3:1]}];
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ReadCbB <= MemCbB[{ReadBank, DataOutAddress[6:5],DataOutAddress[3:1]}];
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ReadCrB <= MemCrB[{DataOutAddress[6:5],DataOutAddress[3:1]}];
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ReadCrB <= MemCrB[{ReadBank, DataOutAddress[6:5],DataOutAddress[3:1]}];
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end // always @ (posedge clk)
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end
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assign DataOutEnable = (WriteBank != ReadBank);
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assign DataOutY = (RegAdrs[6] ==1'b0)?ReadYA:ReadYB;
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assign DataOutY = (RegAdrs[6] ==1'b0)?ReadYA:ReadYB;
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assign DataOutCb = (RegAdrs[7] ==1'b0)?ReadCbA:ReadCbB;
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assign DataOutCb = (RegAdrs[7] ==1'b0)?ReadCbA:ReadCbB;
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assign DataOutCr = (RegAdrs[7] ==1'b0)?ReadCrA:ReadCrB;
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assign DataOutCr = (RegAdrs[7] ==1'b0)?ReadCrA:ReadCrB;
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endmodule // jpeg_ycbcr_mem
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endmodule
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