| Line 5... |
Line 5... |
// Project : JPEG Decoder
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// Project : JPEG Decoder
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// Belong to :
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// Belong to :
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// Author : H.Ishihara
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// Author : H.Ishihara
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// E-Mail : hidemi@sweetcafe.jp
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// E-Mail : hidemi@sweetcafe.jp
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// HomePage : http://www.sweetcafe.jp/
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// HomePage : http://www.sweetcafe.jp/
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// Date : 2006/10/01
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// Date : 2008/03/05
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// Rev. : 1.1
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// Rev. : 2.00
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Rev. Date Description
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// Rev. Date Description
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// 1.01 2006/10/01 1st Release
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// 1.01 2006/10/01 1st Release
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//---------------------------------------------------------------------------
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// 2.00 2008/03/05 Replace to Memory from D-FFs.
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// $Id:
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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`timescale 1ps / 1ps
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`timescale 1ps / 1ps
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module jpeg_ziguzagu
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module jpeg_ziguzagu(
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(
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rst,
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rst,
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clk,
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clk,
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DataInit,
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HuffmanEndEnable,
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DataInEnable,
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DataInEnable,
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DataInAddress,
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DataInAddress,
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DataInColor,
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DataInColor,
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DataInIdle,
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DataInIdle,
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DataIn,
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DataIn,
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HaffumanEndEnable,
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|
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DataOutEnable,
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DataOutEnable,
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DataOutRead,
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DataOutAddress,
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DataOutColor,
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DataOutColor,
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DataOutSel,
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DataOutA,
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Data00Reg,
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DataOutB
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Data01Reg,
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Data02Reg,
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Data03Reg,
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Data04Reg,
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Data05Reg,
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Data06Reg,
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Data07Reg,
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Data08Reg,
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Data09Reg,
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Data10Reg,
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Data11Reg,
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Data12Reg,
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Data13Reg,
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Data14Reg,
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Data15Reg,
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Data16Reg,
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Data17Reg,
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Data18Reg,
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Data19Reg,
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Data20Reg,
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Data21Reg,
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Data22Reg,
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Data23Reg,
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Data24Reg,
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Data25Reg,
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Data26Reg,
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Data27Reg,
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Data28Reg,
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Data29Reg,
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Data30Reg,
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Data31Reg,
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Data32Reg,
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Data33Reg,
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Data34Reg,
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Data35Reg,
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Data36Reg,
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Data37Reg,
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Data38Reg,
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Data39Reg,
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Data40Reg,
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Data41Reg,
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Data42Reg,
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Data43Reg,
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Data44Reg,
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Data45Reg,
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Data46Reg,
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Data47Reg,
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Data48Reg,
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Data49Reg,
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Data50Reg,
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Data51Reg,
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Data52Reg,
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Data53Reg,
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Data54Reg,
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Data55Reg,
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Data56Reg,
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Data57Reg,
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Data58Reg,
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Data59Reg,
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Data60Reg,
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Data61Reg,
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Data62Reg,
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Data63Reg,
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BankARelease,
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BankBRelease
|
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);
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);
|
|
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input clk;
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input clk;
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input rst;
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input rst;
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input DataInit;
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input HuffmanEndEnable;
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input DataInEnable;
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input DataInEnable;
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input [5:0] DataInAddress;
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input [5:0] DataInAddress;
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input [2:0] DataInColor;
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input [2:0] DataInColor;
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output DataInIdle;
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output DataInIdle;
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input [15:0] DataIn;
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input [15:0] DataIn;
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input HaffumanEndEnable;
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output DataOutEnable;
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output DataOutEnable;
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input DataOutRead;
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input [4:0] DataOutAddress;
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output [2:0] DataOutColor;
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output [2:0] DataOutColor;
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input DataOutSel;
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output [15:0] DataOutA;
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output [15:0] Data00Reg;
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output [15:0] DataOutB;
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output [15:0] Data01Reg;
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output [15:0] Data02Reg;
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// State Machine Parameter
|
output [15:0] Data03Reg;
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parameter S_IDLE = 2'd0;
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output [15:0] Data04Reg;
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parameter S_VALID = 2'd1;
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output [15:0] Data05Reg;
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parameter S_FULL = 2'd2;
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output [15:0] Data06Reg;
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parameter S_INIT = 2'd3;
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output [15:0] Data07Reg;
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output [15:0] Data08Reg;
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reg [1:0] State;
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output [15:0] Data09Reg;
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reg [1:0] BankCount;
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output [15:0] Data10Reg;
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output [15:0] Data11Reg;
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output [15:0] Data12Reg;
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output [15:0] Data13Reg;
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output [15:0] Data14Reg;
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output [15:0] Data15Reg;
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output [15:0] Data16Reg;
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output [15:0] Data17Reg;
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output [15:0] Data18Reg;
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output [15:0] Data19Reg;
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output [15:0] Data20Reg;
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output [15:0] Data21Reg;
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output [15:0] Data22Reg;
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output [15:0] Data23Reg;
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output [15:0] Data24Reg;
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output [15:0] Data25Reg;
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output [15:0] Data26Reg;
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output [15:0] Data27Reg;
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output [15:0] Data28Reg;
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output [15:0] Data29Reg;
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output [15:0] Data30Reg;
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output [15:0] Data31Reg;
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output [15:0] Data32Reg;
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output [15:0] Data33Reg;
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output [15:0] Data34Reg;
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output [15:0] Data35Reg;
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output [15:0] Data36Reg;
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output [15:0] Data37Reg;
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output [15:0] Data38Reg;
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output [15:0] Data39Reg;
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output [15:0] Data40Reg;
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output [15:0] Data41Reg;
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output [15:0] Data42Reg;
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output [15:0] Data43Reg;
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output [15:0] Data44Reg;
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output [15:0] Data45Reg;
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output [15:0] Data46Reg;
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output [15:0] Data47Reg;
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output [15:0] Data48Reg;
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output [15:0] Data49Reg;
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output [15:0] Data50Reg;
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output [15:0] Data51Reg;
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output [15:0] Data52Reg;
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output [15:0] Data53Reg;
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output [15:0] Data54Reg;
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output [15:0] Data55Reg;
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output [15:0] Data56Reg;
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output [15:0] Data57Reg;
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output [15:0] Data58Reg;
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output [15:0] Data59Reg;
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output [15:0] Data60Reg;
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output [15:0] Data61Reg;
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output [15:0] Data62Reg;
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output [15:0] Data63Reg;
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input BankARelease;
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input BankBRelease;
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reg BankAEnable;
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reg BankBEnable;
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reg DataInBank;
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reg [2:0] BankAColor;
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reg [2:0] BankColor [0:3];
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reg [2:0] BankBColor;
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reg [1:0] WriteBank;
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reg [1:0] ReadBank;
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wire [5:0] WriteQuery;
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// State Machine
|
always @(posedge clk or negedge rst) begin
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always @(posedge clk or negedge rst) begin
|
if(!rst) begin
|
if(!rst) begin
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BankAEnable <= 1'b0;
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State <= S_IDLE;
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BankBEnable <= 1'b0;
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BankCount <= 2'd0;
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BankAColor <= 3'b000;
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end else begin
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BankBColor <= 3'b000;
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case(State)
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DataInBank <= 1'b0;
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S_IDLE: begin
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end else begin
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if(DataInit) begin
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if(BankAEnable == 1'b0 & DataInBank == 1'b0) begin
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State <= S_INIT;
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if(HaffumanEndEnable == 1'b1 & DataInIdle == 1'b1) begin
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end else if(HuffmanEndEnable) begin
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BankAEnable <= 1'b1;
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State <= S_VALID;
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BankAColor <= DataInColor;
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BankCount <= 2'd0;
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end
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end
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end else begin
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end
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if(BankARelease == 1'b1) begin
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S_VALID: begin
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BankAEnable <= 1'b0;
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if(HuffmanEndEnable && !(DataOutRead && (DataOutAddress == 5'd31))) begin
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end
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if(BankCount == 2'd2) begin
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end
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State <= S_FULL;
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if(BankBEnable == 1'b0 & DataInBank == 1'b1) begin
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BankCount <= 2'd3;
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if(HaffumanEndEnable == 1'b1 & DataInIdle == 1'b1) begin
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end else begin
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BankBEnable <= 1'b1;
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BankCount <= BankCount + 2'd1;
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BankBColor <= DataInColor;
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end
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end
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end else if(!HuffmanEndEnable && (DataOutRead && (DataOutAddress == 5'd31))) begin
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end else begin
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if(BankCount == 2'd0) begin
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if(BankBRelease == 1'b1) begin
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State <= S_IDLE;
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BankBEnable <= 1'b0;
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BankCount <= 2'd0;
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end
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end else begin
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end
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BankCount <= BankCount - 2'd1;
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if(HaffumanEndEnable == 1'b1) begin
|
end
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DataInBank <= ~DataInBank;
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end
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end
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end
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end // else: !if(!rst)
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S_FULL: begin
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end // always @ (posedge clk or negedge rst)
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if(DataOutRead && (DataOutAddress == 5'd31)) begin
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State <= S_VALID;
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assign DataInIdle = BankAEnable == 1'b0 | BankBEnable == 1'b0;
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BankCount <= 2'd2;
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assign DataOutEnable = BankAEnable == 1'b1 | BankBEnable == 1'b1;
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end
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assign DataOutColor = (DataInBank)?BankBColor:BankAColor;
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end
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S_INIT: begin
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wire ZigAEnable;
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State <= S_IDLE;
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wire ZigBEnable;
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end
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endcase
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wire [15:0] BankA00Reg;
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end
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wire [15:0] BankA01Reg;
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end
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wire [15:0] BankA02Reg;
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wire [15:0] BankA03Reg;
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wire [15:0] BankA04Reg;
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wire [15:0] BankA05Reg;
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wire [15:0] BankA06Reg;
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wire [15:0] BankA07Reg;
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wire [15:0] BankA08Reg;
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wire [15:0] BankA09Reg;
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wire [15:0] BankA10Reg;
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wire [15:0] BankA11Reg;
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wire [15:0] BankA12Reg;
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wire [15:0] BankA13Reg;
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wire [15:0] BankA14Reg;
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wire [15:0] BankA15Reg;
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wire [15:0] BankA16Reg;
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wire [15:0] BankA17Reg;
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wire [15:0] BankA18Reg;
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wire [15:0] BankA19Reg;
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wire [15:0] BankA20Reg;
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wire [15:0] BankA21Reg;
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wire [15:0] BankA22Reg;
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wire [15:0] BankA23Reg;
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wire [15:0] BankA24Reg;
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wire [15:0] BankA25Reg;
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wire [15:0] BankA26Reg;
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wire [15:0] BankA27Reg;
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wire [15:0] BankA28Reg;
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wire [15:0] BankA29Reg;
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wire [15:0] BankA30Reg;
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wire [15:0] BankA31Reg;
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wire [15:0] BankA32Reg;
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wire [15:0] BankA33Reg;
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wire [15:0] BankA34Reg;
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wire [15:0] BankA35Reg;
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wire [15:0] BankA36Reg;
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wire [15:0] BankA37Reg;
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wire [15:0] BankA38Reg;
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wire [15:0] BankA39Reg;
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wire [15:0] BankA40Reg;
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wire [15:0] BankA41Reg;
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wire [15:0] BankA42Reg;
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wire [15:0] BankA43Reg;
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wire [15:0] BankA44Reg;
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wire [15:0] BankA45Reg;
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wire [15:0] BankA46Reg;
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wire [15:0] BankA47Reg;
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wire [15:0] BankA48Reg;
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wire [15:0] BankA49Reg;
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wire [15:0] BankA50Reg;
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wire [15:0] BankA51Reg;
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wire [15:0] BankA52Reg;
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wire [15:0] BankA53Reg;
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wire [15:0] BankA54Reg;
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wire [15:0] BankA55Reg;
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wire [15:0] BankA56Reg;
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wire [15:0] BankA57Reg;
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wire [15:0] BankA58Reg;
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wire [15:0] BankA59Reg;
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wire [15:0] BankA60Reg;
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wire [15:0] BankA61Reg;
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wire [15:0] BankA62Reg;
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wire [15:0] BankA63Reg;
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wire [15:0] BankB00Reg;
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wire [15:0] BankB01Reg;
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wire [15:0] BankB02Reg;
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wire [15:0] BankB03Reg;
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wire [15:0] BankB04Reg;
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wire [15:0] BankB05Reg;
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wire [15:0] BankB06Reg;
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wire [15:0] BankB07Reg;
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wire [15:0] BankB08Reg;
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wire [15:0] BankB09Reg;
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wire [15:0] BankB10Reg;
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wire [15:0] BankB11Reg;
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wire [15:0] BankB12Reg;
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wire [15:0] BankB13Reg;
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wire [15:0] BankB14Reg;
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wire [15:0] BankB15Reg;
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wire [15:0] BankB16Reg;
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wire [15:0] BankB17Reg;
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wire [15:0] BankB18Reg;
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wire [15:0] BankB19Reg;
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wire [15:0] BankB20Reg;
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wire [15:0] BankB21Reg;
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wire [15:0] BankB22Reg;
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wire [15:0] BankB23Reg;
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wire [15:0] BankB24Reg;
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wire [15:0] BankB25Reg;
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wire [15:0] BankB26Reg;
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wire [15:0] BankB27Reg;
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wire [15:0] BankB28Reg;
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wire [15:0] BankB29Reg;
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wire [15:0] BankB30Reg;
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wire [15:0] BankB31Reg;
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wire [15:0] BankB32Reg;
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wire [15:0] BankB33Reg;
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wire [15:0] BankB34Reg;
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wire [15:0] BankB35Reg;
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wire [15:0] BankB36Reg;
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wire [15:0] BankB37Reg;
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wire [15:0] BankB38Reg;
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wire [15:0] BankB39Reg;
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wire [15:0] BankB40Reg;
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wire [15:0] BankB41Reg;
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wire [15:0] BankB42Reg;
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wire [15:0] BankB43Reg;
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wire [15:0] BankB44Reg;
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wire [15:0] BankB45Reg;
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wire [15:0] BankB46Reg;
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wire [15:0] BankB47Reg;
|
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wire [15:0] BankB48Reg;
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wire [15:0] BankB49Reg;
|
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wire [15:0] BankB50Reg;
|
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wire [15:0] BankB51Reg;
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wire [15:0] BankB52Reg;
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wire [15:0] BankB53Reg;
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wire [15:0] BankB54Reg;
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wire [15:0] BankB55Reg;
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wire [15:0] BankB56Reg;
|
|
wire [15:0] BankB57Reg;
|
|
wire [15:0] BankB58Reg;
|
|
wire [15:0] BankB59Reg;
|
|
wire [15:0] BankB60Reg;
|
|
wire [15:0] BankB61Reg;
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wire [15:0] BankB62Reg;
|
|
wire [15:0] BankB63Reg;
|
|
|
|
assign ZigAEnable = DataInEnable == 1'b1 & DataInBank == 1'b0;
|
|
assign ZigBEnable = DataInEnable == 1'b1 & DataInBank == 1'b1;
|
|
|
|
jpeg_ziguzagu_reg u_jpeg_ziguzagu_reg0(
|
|
.rst(rst),
|
|
.clk(clk),
|
|
|
|
.DataInEnable ( ZigAEnable ),
|
|
.DataInAddress ( DataInAddress ),
|
|
.DataIn ( DataIn ),
|
|
|
|
.Data00Reg( BankA00Reg ),
|
|
.Data01Reg( BankA01Reg ),
|
|
.Data02Reg( BankA02Reg ),
|
|
.Data03Reg( BankA03Reg ),
|
|
.Data04Reg( BankA04Reg ),
|
|
.Data05Reg( BankA05Reg ),
|
|
.Data06Reg( BankA06Reg ),
|
|
.Data07Reg( BankA07Reg ),
|
|
.Data08Reg( BankA08Reg ),
|
|
.Data09Reg( BankA09Reg ),
|
|
.Data10Reg( BankA10Reg ),
|
|
.Data11Reg( BankA11Reg ),
|
|
.Data12Reg( BankA12Reg ),
|
|
.Data13Reg( BankA13Reg ),
|
|
.Data14Reg( BankA14Reg ),
|
|
.Data15Reg( BankA15Reg ),
|
|
.Data16Reg( BankA16Reg ),
|
|
.Data17Reg( BankA17Reg ),
|
|
.Data18Reg( BankA18Reg ),
|
|
.Data19Reg( BankA19Reg ),
|
|
.Data20Reg( BankA20Reg ),
|
|
.Data21Reg( BankA21Reg ),
|
|
.Data22Reg( BankA22Reg ),
|
|
.Data23Reg( BankA23Reg ),
|
|
.Data24Reg( BankA24Reg ),
|
|
.Data25Reg( BankA25Reg ),
|
|
.Data26Reg( BankA26Reg ),
|
|
.Data27Reg( BankA27Reg ),
|
|
.Data28Reg( BankA28Reg ),
|
|
.Data29Reg( BankA29Reg ),
|
|
.Data30Reg( BankA30Reg ),
|
|
.Data31Reg( BankA31Reg ),
|
|
.Data32Reg( BankA32Reg ),
|
|
.Data33Reg( BankA33Reg ),
|
|
.Data34Reg( BankA34Reg ),
|
|
.Data35Reg( BankA35Reg ),
|
|
.Data36Reg( BankA36Reg ),
|
|
.Data37Reg( BankA37Reg ),
|
|
.Data38Reg( BankA38Reg ),
|
|
.Data39Reg( BankA39Reg ),
|
|
.Data40Reg( BankA40Reg ),
|
|
.Data41Reg( BankA41Reg ),
|
|
.Data42Reg( BankA42Reg ),
|
|
.Data43Reg( BankA43Reg ),
|
|
.Data44Reg( BankA44Reg ),
|
|
.Data45Reg( BankA45Reg ),
|
|
.Data46Reg( BankA46Reg ),
|
|
.Data47Reg( BankA47Reg ),
|
|
.Data48Reg( BankA48Reg ),
|
|
.Data49Reg( BankA49Reg ),
|
|
.Data50Reg( BankA50Reg ),
|
|
.Data51Reg( BankA51Reg ),
|
|
.Data52Reg( BankA52Reg ),
|
|
.Data53Reg( BankA53Reg ),
|
|
.Data54Reg( BankA54Reg ),
|
|
.Data55Reg( BankA55Reg ),
|
|
.Data56Reg( BankA56Reg ),
|
|
.Data57Reg( BankA57Reg ),
|
|
.Data58Reg( BankA58Reg ),
|
|
.Data59Reg( BankA59Reg ),
|
|
.Data60Reg( BankA60Reg ),
|
|
.Data61Reg( BankA61Reg ),
|
|
.Data62Reg( BankA62Reg ),
|
|
.Data63Reg( BankA63Reg )
|
|
);
|
|
|
|
jpeg_ziguzagu_reg u_jpeg_ziguzagu_reg1(
|
// Color
|
.rst(rst),
|
always @(posedge clk or negedge rst) begin
|
.clk(clk),
|
if(!rst) begin
|
|
BankColor[0] <= 3'd0;
|
.DataInEnable ( ZigBEnable ),
|
BankColor[1] <= 3'd0;
|
.DataInAddress ( DataInAddress ),
|
BankColor[2] <= 3'd0;
|
.DataIn ( DataIn ),
|
BankColor[3] <= 3'd0;
|
|
end else begin
|
.Data00Reg( BankB00Reg ),
|
if(HuffmanEndEnable) BankColor[WriteBank] <= DataInColor;
|
.Data01Reg( BankB01Reg ),
|
end
|
.Data02Reg( BankB02Reg ),
|
end
|
.Data03Reg( BankB03Reg ),
|
|
.Data04Reg( BankB04Reg ),
|
// Bank
|
.Data05Reg( BankB05Reg ),
|
always @(posedge clk or negedge rst) begin
|
.Data06Reg( BankB06Reg ),
|
if(!rst) begin
|
.Data07Reg( BankB07Reg ),
|
WriteBank <= 2'd0;
|
.Data08Reg( BankB08Reg ),
|
ReadBank <= 2'd0;
|
.Data09Reg( BankB09Reg ),
|
end else begin
|
.Data10Reg( BankB10Reg ),
|
// Write Bank
|
.Data11Reg( BankB11Reg ),
|
if(State == S_INIT) begin
|
.Data12Reg( BankB12Reg ),
|
WriteBank <= 2'd0;
|
.Data13Reg( BankB13Reg ),
|
end else if(HuffmanEndEnable) begin
|
.Data14Reg( BankB14Reg ),
|
WriteBank <= WriteBank + 2'd1;
|
.Data15Reg( BankB15Reg ),
|
end
|
.Data16Reg( BankB16Reg ),
|
// Read Bank
|
.Data17Reg( BankB17Reg ),
|
if(State == S_INIT) begin
|
.Data18Reg( BankB18Reg ),
|
ReadBank <= 2'd0;
|
.Data19Reg( BankB19Reg ),
|
end else if(DataOutRead && (DataOutAddress == 5'd31)) begin
|
.Data20Reg( BankB20Reg ),
|
ReadBank <= ReadBank + 2'd1;
|
.Data21Reg( BankB21Reg ),
|
end
|
.Data22Reg( BankB22Reg ),
|
end
|
.Data23Reg( BankB23Reg ),
|
end
|
.Data24Reg( BankB24Reg ),
|
|
.Data25Reg( BankB25Reg ),
|
// Make a Write Address
|
.Data26Reg( BankB26Reg ),
|
function [5:0] F_WriteQuery;
|
.Data27Reg( BankB27Reg ),
|
input [5:0] Count;
|
.Data28Reg( BankB28Reg ),
|
case(Count)
|
.Data29Reg( BankB29Reg ),
|
6'd0: F_WriteQuery = {1'b0, 5'd0 };
|
.Data30Reg( BankB30Reg ),
|
6'd1: F_WriteQuery = {1'b0, 5'd2 };
|
.Data31Reg( BankB31Reg ),
|
6'd2: F_WriteQuery = {1'b0, 5'd4 };
|
.Data32Reg( BankB32Reg ),
|
6'd3: F_WriteQuery = {1'b0, 5'd8 };
|
.Data33Reg( BankB33Reg ),
|
6'd4: F_WriteQuery = {1'b0, 5'd6 };
|
.Data34Reg( BankB34Reg ),
|
6'd5: F_WriteQuery = {1'b0, 5'd1 };
|
.Data35Reg( BankB35Reg ),
|
6'd6: F_WriteQuery = {1'b1, 5'd3 };
|
.Data36Reg( BankB36Reg ),
|
6'd7: F_WriteQuery = {1'b0, 5'd5 };
|
.Data37Reg( BankB37Reg ),
|
6'd8: F_WriteQuery = {1'b0, 5'd10};
|
.Data38Reg( BankB38Reg ),
|
6'd9: F_WriteQuery = {1'b0, 5'd12};
|
.Data39Reg( BankB39Reg ),
|
6'd10: F_WriteQuery = {1'b0, 5'd16};
|
.Data40Reg( BankB40Reg ),
|
6'd11: F_WriteQuery = {1'b0, 5'd14};
|
.Data41Reg( BankB41Reg ),
|
6'd12: F_WriteQuery = {1'b0, 5'd9 };
|
.Data42Reg( BankB42Reg ),
|
6'd13: F_WriteQuery = {1'b1, 5'd7 };
|
.Data43Reg( BankB43Reg ),
|
6'd14: F_WriteQuery = {1'b1, 5'd0 };
|
.Data44Reg( BankB44Reg ),
|
6'd15: F_WriteQuery = {1'b0, 5'd3 };
|
.Data45Reg( BankB45Reg ),
|
6'd16: F_WriteQuery = {1'b1, 5'd4 };
|
.Data46Reg( BankB46Reg ),
|
6'd17: F_WriteQuery = {1'b1, 5'd11};
|
.Data47Reg( BankB47Reg ),
|
6'd18: F_WriteQuery = {1'b0, 5'd13};
|
.Data48Reg( BankB48Reg ),
|
6'd19: F_WriteQuery = {1'b0, 5'd18};
|
.Data49Reg( BankB49Reg ),
|
6'd20: F_WriteQuery = {1'b0, 5'd20};
|
.Data50Reg( BankB50Reg ),
|
6'd21: F_WriteQuery = {1'b0, 5'd24};
|
.Data51Reg( BankB51Reg ),
|
6'd22: F_WriteQuery = {1'b0, 5'd22};
|
.Data52Reg( BankB52Reg ),
|
6'd23: F_WriteQuery = {1'b0, 5'd17};
|
.Data53Reg( BankB53Reg ),
|
6'd24: F_WriteQuery = {1'b1, 5'd15};
|
.Data54Reg( BankB54Reg ),
|
6'd25: F_WriteQuery = {1'b1, 5'd8 };
|
.Data55Reg( BankB55Reg ),
|
6'd26: F_WriteQuery = {1'b0, 5'd7 };
|
.Data56Reg( BankB56Reg ),
|
6'd27: F_WriteQuery = {1'b1, 5'd1 };
|
.Data57Reg( BankB57Reg ),
|
6'd28: F_WriteQuery = {1'b1, 5'd2 };
|
.Data58Reg( BankB58Reg ),
|
6'd29: F_WriteQuery = {1'b1, 5'd5 };
|
.Data59Reg( BankB59Reg ),
|
6'd30: F_WriteQuery = {1'b0, 5'd11};
|
.Data60Reg( BankB60Reg ),
|
6'd31: F_WriteQuery = {1'b1, 5'd12};
|
.Data61Reg( BankB61Reg ),
|
6'd32: F_WriteQuery = {1'b1, 5'd19};
|
.Data62Reg( BankB62Reg ),
|
6'd33: F_WriteQuery = {1'b0, 5'd21};
|
.Data63Reg( BankB63Reg )
|
6'd34: F_WriteQuery = {1'b0, 5'd26};
|
);
|
6'd35: F_WriteQuery = {1'b0, 5'd28};
|
|
6'd36: F_WriteQuery = {1'b0, 5'd30};
|
|
6'd37: F_WriteQuery = {1'b0, 5'd25};
|
|
6'd38: F_WriteQuery = {1'b1, 5'd23};
|
|
6'd39: F_WriteQuery = {1'b1, 5'd16};
|
|
6'd40: F_WriteQuery = {1'b0, 5'd15};
|
|
6'd41: F_WriteQuery = {1'b1, 5'd9 };
|
|
6'd42: F_WriteQuery = {1'b1, 5'd6 };
|
|
6'd43: F_WriteQuery = {1'b1, 5'd10};
|
|
6'd44: F_WriteQuery = {1'b1, 5'd13};
|
|
6'd45: F_WriteQuery = {1'b0, 5'd19};
|
|
6'd46: F_WriteQuery = {1'b1, 5'd20};
|
|
6'd47: F_WriteQuery = {1'b1, 5'd27};
|
|
6'd48: F_WriteQuery = {1'b0, 5'd29};
|
|
6'd49: F_WriteQuery = {1'b1, 5'd31};
|
|
6'd50: F_WriteQuery = {1'b1, 5'd24};
|
|
6'd51: F_WriteQuery = {1'b0, 5'd23};
|
|
6'd52: F_WriteQuery = {1'b1, 5'd17};
|
|
6'd53: F_WriteQuery = {1'b1, 5'd14};
|
|
6'd54: F_WriteQuery = {1'b1, 5'd18};
|
|
6'd55: F_WriteQuery = {1'b1, 5'd21};
|
|
6'd56: F_WriteQuery = {1'b0, 5'd27};
|
|
6'd57: F_WriteQuery = {1'b1, 5'd28};
|
|
6'd58: F_WriteQuery = {1'b0, 5'd31};
|
|
6'd59: F_WriteQuery = {1'b1, 5'd25};
|
|
6'd60: F_WriteQuery = {1'b1, 5'd22};
|
|
6'd61: F_WriteQuery = {1'b1, 5'd26};
|
|
6'd62: F_WriteQuery = {1'b1, 5'd29};
|
|
6'd63: F_WriteQuery = {1'b1, 5'd30};
|
|
endcase
|
|
endfunction
|
|
|
|
assign WriteQuery = F_WriteQuery(DataInAddress);
|
|
|
|
// RAM(16bit x 32word x 2Bank)
|
|
reg [15:0] MemoryA [0:127];
|
|
reg [15:0] MemoryB [0:127];
|
|
|
|
wire [6:0] WriteAddress;
|
|
wire WriteEnableA, WriteEnableB;
|
|
|
|
assign WriteEnableA = DataInEnable & ~WriteQuery[5];
|
|
assign WriteEnableB = DataInEnable & WriteQuery[5];
|
|
assign WriteAddress = {WriteBank, WriteQuery[4:0]};
|
|
|
|
// Port A(Write Only)
|
|
always @(posedge clk) begin
|
|
if(WriteEnableA) MemoryA[WriteAddress] <= DataIn;
|
|
if(WriteEnableB) MemoryB[WriteAddress] <= DataIn;
|
|
end
|
|
|
|
reg [15:0] RegMemoryA, RegMemoryB;
|
|
|
|
// Port B(Read/Wirte)
|
|
always @(posedge clk) begin
|
|
RegMemoryA <= MemoryA[{ReadBank, DataOutAddress}];
|
|
RegMemoryB <= MemoryB[{ReadBank, DataOutAddress}];
|
|
end
|
|
|
|
// Data Enable Register
|
|
reg [127:0] DataEnableA, DataEnableB;
|
|
|
|
always @(posedge clk or negedge rst) begin
|
|
if(!rst) begin
|
|
DataEnableA <= 128'd0;
|
|
DataEnableB <= 128'd0;
|
|
end else begin
|
|
if(State == S_INIT) begin
|
|
DataEnableA <= 128'd0;
|
|
DataEnableB <= 128'd0;
|
|
end else begin
|
|
if(DataInEnable && (WriteBank == 2'd0)) begin
|
|
if(WriteEnableA) begin
|
|
if(WriteAddress[4:0] == 5'd0) begin
|
|
DataEnableA[{2'd0, WriteAddress[4:0]}] <= 1'b1;
|
|
DataEnableA[31:1] <= 31'd0;
|
|
DataEnableB[31:0] <= 32'd0;
|
|
end else begin
|
|
DataEnableA[{2'd0, WriteAddress[4:0]}] <= 1'b1;
|
|
end
|
|
end else begin
|
|
DataEnableB[{2'd0, WriteAddress[4:0]}] <= 1'b1;
|
|
end
|
|
end
|
|
if(DataInEnable && (WriteBank == 2'd1)) begin
|
|
if(WriteEnableA) begin
|
|
if(WriteAddress[4:0] == 5'd0) begin
|
|
DataEnableA[{2'd1, WriteAddress[4:0]}] <= 1'b1;
|
|
DataEnableA[63:33] <= 31'd0;
|
|
DataEnableB[63:32] <= 32'd0;
|
|
end else begin
|
|
DataEnableA[{2'd1, WriteAddress[4:0]}] <= 1'b1;
|
|
end
|
|
end else begin
|
|
DataEnableB[{2'd1, WriteAddress[4:0]}] <= 1'b1;
|
|
end
|
|
end
|
|
if(DataInEnable && (WriteBank == 2'd2)) begin
|
|
if(WriteEnableA) begin
|
|
if(WriteAddress[4:0] == 5'd0) begin
|
|
DataEnableA[{2'd2, WriteAddress[4:0]}] <= 1'b1;
|
|
DataEnableA[95:65] <= 31'd0;
|
|
DataEnableB[95:64] <= 32'd0;
|
|
end else begin
|
|
DataEnableA[{2'd2, WriteAddress[4:0]}] <= 1'b1;
|
|
end
|
|
end else begin
|
|
DataEnableB[{2'd2, WriteAddress[4:0]}] <= 1'b1;
|
|
end
|
|
end
|
|
if(DataInEnable && (WriteBank == 2'd3)) begin
|
|
if(WriteEnableA) begin
|
|
if(WriteAddress[4:0] == 5'd0) begin
|
|
DataEnableA[{2'd3, WriteAddress[4:0]}] <= 1'b1;
|
|
DataEnableA[127:97] <= 31'd0;
|
|
DataEnableB[127:96] <= 32'd0;
|
|
end else begin
|
|
DataEnableA[{2'd3, WriteAddress[4:0]}] <= 1'b1;
|
|
end
|
|
end else begin
|
|
DataEnableB[{2'd3, WriteAddress[4:0]}] <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
reg AddressDelayA, AddressDelayB;
|
|
|
|
always @(posedge clk or negedge rst) begin
|
|
if(!rst) begin
|
|
AddressDelayA <= 1'b0;
|
|
AddressDelayB <= 1'b0;
|
|
end else begin
|
|
AddressDelayA <= DataEnableA[{ReadBank, DataOutAddress}];
|
|
AddressDelayB <= DataEnableB[{ReadBank, DataOutAddress}];
|
|
end
|
|
end
|
|
|
assign Data00Reg = (DataOutSel)?BankB00Reg:BankA00Reg;
|
// Output Signal
|
assign Data01Reg = (DataOutSel)?BankB01Reg:BankA01Reg;
|
assign DataInIdle = (State == S_IDLE) | (State == S_VALID);
|
assign Data02Reg = (DataOutSel)?BankB02Reg:BankA02Reg;
|
assign DataOutEnable = (State == S_VALID) | (State == S_FULL);
|
assign Data03Reg = (DataOutSel)?BankB03Reg:BankA03Reg;
|
assign DataOutColor = BankColor[ReadBank];
|
assign Data04Reg = (DataOutSel)?BankB04Reg:BankA04Reg;
|
assign DataOutA = (AddressDelayA)?RegMemoryA:16'd0;
|
assign Data05Reg = (DataOutSel)?BankB05Reg:BankA05Reg;
|
assign DataOutB = (AddressDelayB)?RegMemoryB:16'd0;
|
assign Data06Reg = (DataOutSel)?BankB06Reg:BankA06Reg;
|
|
assign Data07Reg = (DataOutSel)?BankB07Reg:BankA07Reg;
|
|
assign Data08Reg = (DataOutSel)?BankB08Reg:BankA08Reg;
|
|
assign Data09Reg = (DataOutSel)?BankB09Reg:BankA09Reg;
|
|
assign Data10Reg = (DataOutSel)?BankB10Reg:BankA10Reg;
|
|
assign Data11Reg = (DataOutSel)?BankB11Reg:BankA11Reg;
|
|
assign Data12Reg = (DataOutSel)?BankB12Reg:BankA12Reg;
|
|
assign Data13Reg = (DataOutSel)?BankB13Reg:BankA13Reg;
|
|
assign Data14Reg = (DataOutSel)?BankB14Reg:BankA14Reg;
|
|
assign Data15Reg = (DataOutSel)?BankB15Reg:BankA15Reg;
|
|
assign Data16Reg = (DataOutSel)?BankB16Reg:BankA16Reg;
|
|
assign Data17Reg = (DataOutSel)?BankB17Reg:BankA17Reg;
|
|
assign Data18Reg = (DataOutSel)?BankB18Reg:BankA18Reg;
|
|
assign Data19Reg = (DataOutSel)?BankB19Reg:BankA19Reg;
|
|
assign Data20Reg = (DataOutSel)?BankB20Reg:BankA20Reg;
|
|
assign Data21Reg = (DataOutSel)?BankB21Reg:BankA21Reg;
|
|
assign Data22Reg = (DataOutSel)?BankB22Reg:BankA22Reg;
|
|
assign Data23Reg = (DataOutSel)?BankB23Reg:BankA23Reg;
|
|
assign Data24Reg = (DataOutSel)?BankB24Reg:BankA24Reg;
|
|
assign Data25Reg = (DataOutSel)?BankB25Reg:BankA25Reg;
|
|
assign Data26Reg = (DataOutSel)?BankB26Reg:BankA26Reg;
|
|
assign Data27Reg = (DataOutSel)?BankB27Reg:BankA27Reg;
|
|
assign Data28Reg = (DataOutSel)?BankB28Reg:BankA28Reg;
|
|
assign Data29Reg = (DataOutSel)?BankB29Reg:BankA29Reg;
|
|
assign Data30Reg = (DataOutSel)?BankB30Reg:BankA30Reg;
|
|
assign Data31Reg = (DataOutSel)?BankB31Reg:BankA31Reg;
|
|
assign Data32Reg = (DataOutSel)?BankB32Reg:BankA32Reg;
|
|
assign Data33Reg = (DataOutSel)?BankB33Reg:BankA33Reg;
|
|
assign Data34Reg = (DataOutSel)?BankB34Reg:BankA34Reg;
|
|
assign Data35Reg = (DataOutSel)?BankB35Reg:BankA35Reg;
|
|
assign Data36Reg = (DataOutSel)?BankB36Reg:BankA36Reg;
|
|
assign Data37Reg = (DataOutSel)?BankB37Reg:BankA37Reg;
|
|
assign Data38Reg = (DataOutSel)?BankB38Reg:BankA38Reg;
|
|
assign Data39Reg = (DataOutSel)?BankB39Reg:BankA39Reg;
|
|
assign Data40Reg = (DataOutSel)?BankB40Reg:BankA40Reg;
|
|
assign Data41Reg = (DataOutSel)?BankB41Reg:BankA41Reg;
|
|
assign Data42Reg = (DataOutSel)?BankB42Reg:BankA42Reg;
|
|
assign Data43Reg = (DataOutSel)?BankB43Reg:BankA43Reg;
|
|
assign Data44Reg = (DataOutSel)?BankB44Reg:BankA44Reg;
|
|
assign Data45Reg = (DataOutSel)?BankB45Reg:BankA45Reg;
|
|
assign Data46Reg = (DataOutSel)?BankB46Reg:BankA46Reg;
|
|
assign Data47Reg = (DataOutSel)?BankB47Reg:BankA47Reg;
|
|
assign Data48Reg = (DataOutSel)?BankB48Reg:BankA48Reg;
|
|
assign Data49Reg = (DataOutSel)?BankB49Reg:BankA49Reg;
|
|
assign Data50Reg = (DataOutSel)?BankB50Reg:BankA50Reg;
|
|
assign Data51Reg = (DataOutSel)?BankB51Reg:BankA51Reg;
|
|
assign Data52Reg = (DataOutSel)?BankB52Reg:BankA52Reg;
|
|
assign Data53Reg = (DataOutSel)?BankB53Reg:BankA53Reg;
|
|
assign Data54Reg = (DataOutSel)?BankB54Reg:BankA54Reg;
|
|
assign Data55Reg = (DataOutSel)?BankB55Reg:BankA55Reg;
|
|
assign Data56Reg = (DataOutSel)?BankB56Reg:BankA56Reg;
|
|
assign Data57Reg = (DataOutSel)?BankB57Reg:BankA57Reg;
|
|
assign Data58Reg = (DataOutSel)?BankB58Reg:BankA58Reg;
|
|
assign Data59Reg = (DataOutSel)?BankB59Reg:BankA59Reg;
|
|
assign Data60Reg = (DataOutSel)?BankB60Reg:BankA60Reg;
|
|
assign Data61Reg = (DataOutSel)?BankB61Reg:BankA61Reg;
|
|
assign Data62Reg = (DataOutSel)?BankB62Reg:BankA62Reg;
|
|
assign Data63Reg = (DataOutSel)?BankB63Reg:BankA63Reg;
|
|
|
|
endmodule // jpeg_ziguzagu
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
