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[/] [dmt_tx/] [trunk/] [const_encoder/] [rtl/] [fifo.v] - Diff between revs 13 and 15

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Rev 13 Rev 15
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/* *****************************************************************
/* *****************************************************************
 *
 *
 *  This file is part of Tone Order and Constellation Encoder Core.
 *  This file is part of the
 
 *
 
 *   Tone Order and Constellation Encoder Core.
 
 *
 
 *
 
 * Description:
 
 *
 
 *  fifo is a synchronouys FIFO without write through. The read
 
 *  and write operation happens with the positive edge of the clk
 
 *  signal. If the FIFO is empty and performing a read/write operation
 
 *  with at the same clock cycle only the write operation will succeed.
 
 *  The read operation will not return a valid value.
 
 *
 
 *
 
 *********************************************************************
 *  Copyright (C) 2007 Guenter Dannoritzer
 *  Copyright (C) 2007 Guenter Dannoritzer
 *
 *
 *   This source is free software; you can redistribute it
 *   This source is free software; you can redistribute it
 *   and/or modify it under the terms of the
 *   and/or modify it under the terms of the
 *             GNU General Public License
 *             GNU General Public License
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 *   without even the implied warranty of MERCHANTABILITY
 *   without even the implied warranty of MERCHANTABILITY
 *   or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *   GNU General Public License for more details.
 *
 *
 *   You should have received a copy of the
 *   You should have received a copy of the
 *   GNU General Public License along with this program.
 *   GNU General Public License along with this source.
 *   If not, see <http://www.gnu.org/licenses/>.
 *   If not, see <http://www.gnu.org/licenses/>.
 *
 *
 * *****************************************************************/
 * *****************************************************************/
module fifo(
module fifo(
          clk,
          clk,
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    fill_ctr <= 0;
    fill_ctr <= 0;
  end
  end
  else begin
  else begin
 
 
    // TODO: fix this to allow read/write at one clock cycle
    // TODO: fix this to allow read/write at one clock cycle
    if(dp_we_i) begin
    if(dp_we_i & ~ dp_re_i) begin
      fill_ctr <= fill_ctr + 1;
      fill_ctr <= fill_ctr + 1;
    end
    end
 
    else if(dp_re_i & ~ dp_we_i) begin
    if(dp_re_i) begin
 
      fill_ctr <= fill_ctr - 1;
      fill_ctr <= fill_ctr - 1;
    end
    end
  end
  end
end
end
 
 

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