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[/] [double_fpu/] [trunk/] [pipeline/] [Readme_pipeline.txt] - Diff between revs 6 and 8

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The verilog files, fpu_addsub.v and fpu_mul.v, are pipelined versions of
The verilog files, fpu_addsub.v and fpu_mul.v, are pipelined versions of
floating point operators.  Rounding is not supported by these operators, and
floating point operators.  The four rounding modes (Nearest, To Zero, To
denormalized numbers are treated as 0.  If infinity or NaN is on either of the inputs,
Positive Infintiy, To Negative Infinity) are supported by these operators.
then infinity will be the output.  Both operators, addsub and mul, have a latency
Denormalized numbers are not supported, but instead are treated as 0.
of 18 clock cycles, and then an output is available on each clock cycle after the latency.
If infinity or NaN is on either of the inputs,
 
then infinity will be the output.  Addition and subtraction have a latency
 
of 24 clock cycles, and then an output is available on each clock cycle after the latency.
 
Multiplication has a latency of 21 clock cycles, and
 
then an output is available on each clock cycle after the latency.
 
 
For addition and subtraction, fpu_addsub.v was synthesized with an estimated
For addition and subtraction, fpu_addsub.v was synthesized with an estimated
frequency of 276 MHz for a Virtex5 device.  The synthesis results are below.
frequency of 259 MHz for a Virtex5 device.  The synthesis results are below.
The file, fpu_addsub_TB.v, is the testbench used to simulate fpu_addsub.v.
The file, fpu_addsub_TB.v, is the testbench used to simulate fpu_addsub.v.
 
 
For multiplication, fpu_mul.v was synthesized with an estimated
For multiplication, fpu_mul.v was synthesized with an estimated
frequency of 426 MHz for a Virtex5 device.  The synthesis results are below.
frequency of 393 MHz for a Virtex5 device.  The synthesis results are below.
The file, fpu_mul_TB.v, is the testbench used to simulate fpu_mul.v.
The file, fpu_mul_TB.v, is the testbench used to simulate fpu_mul.v.
 
 
Please email me any questions.
Please email me any questions.
 
 
David Lundgren
David Lundgren
davidklun@gmail.com
davidklun@gmail.com
 
 
addsub synthesis results:
addsub synthesis results:
 
 
---------------------------------------
---------------------------------------
Resource Usage Report for fpu
Resource Usage Report for fpu_addsub
 
 
Mapping to part: xc5vsx95tff1136-2
Mapping to part: xc5vsx95tff1136-2
Cell usage:
Cell usage:
FDE             16 uses
FDE             55 uses
FDR             6 uses
FDR             6 uses
FDRE            2350 uses
FDRE            2848 uses
GND             1 use
GND             1 use
MUXCY           7 uses
MUXCY           8 uses
MUXCY_L         183 uses
MUXCY_L         293 uses
VCC             1 use
VCC             1 use
XORCY           130 uses
XORCY           240 uses
XORCY_L         4 uses
XORCY_L         5 uses
LUT1            14 uses
LUT1            98 uses
LUT2            386 uses
LUT2            377 uses
LUT3            448 uses
LUT3            522 uses
LUT4            133 uses
LUT4            151 uses
LUT5            103 uses
LUT5            101 uses
LUT6            496 uses
LUT6            517 uses
 
 
I/O ports: 197
I/O ports: 199
I/O primitives: 196
I/O primitives: 198
IBUF           131 uses
IBUF           133 uses
OBUF           65 uses
OBUF           65 uses
 
 
BUFGP          1 use
BUFGP          1 use
 
 
SRL primitives:
SRL primitives:
SRL16E         16 uses
SRLC32E        1 use
 
SRL16E         54 uses
 
 
I/O Register bits:                  0
I/O Register bits:                  0
Register bits not including I/Os:   2372 (4%)
Register bits not including I/Os:   2909 (4%)
 
 
Global Clock Buffers: 1 of 32 (3%)
Global Clock Buffers: 1 of 32 (3%)
 
 
Total load per clock:
Total load per clock:
   fpu|clk: 2388
   fpu_addsub|clk: 2964
 
 
Mapping Summary:
Mapping Summary:
Total  LUTs: 1596 (2%)
Total  LUTs: 1821 (3%)
 
 
------------------------------
------------------------------
 
 
multiply synthesis results:
multiply synthesis results:
 
 
Line 69... Line 74...
Resource Usage Report for fpu_mul
Resource Usage Report for fpu_mul
 
 
Mapping to part: xc5vsx95tff1136-2
Mapping to part: xc5vsx95tff1136-2
Cell usage:
Cell usage:
DSP48E          9 uses
DSP48E          9 uses
FDE             80 uses
FDE             83 uses
FDRE            1221 uses
FDRE            1536 uses
FDRSE           11 uses
FDRSE           11 uses
GND             1 use
GND             1 use
MUXCY           4 uses
MUXCY           7 uses
MUXCY_L         82 uses
MUXCY_L         164 uses
VCC             1 use
VCC             1 use
XORCY           75 uses
XORCY           128 uses
XORCY_L         3 uses
XORCY_L         5 uses
LUT1            25 uses
LUT1            82 uses
LUT2            203 uses
LUT2            215 uses
LUT3            57 uses
LUT3            170 uses
LUT4            30 uses
LUT4            48 uses
LUT5            7 uses
LUT5            13 uses
LUT6            14 uses
LUT6            32 uses
 
 
I/O ports: 196
I/O ports: 198
I/O primitives: 195
I/O primitives: 197
IBUF           130 uses
IBUF           132 uses
OBUF           65 uses
OBUF           65 uses
 
 
BUFGP          1 use
BUFGP          1 use
 
 
SRL primitives:
SRL primitives:
SRLC32E        1 use
SRL16E         83 uses
SRL16E         27 uses
 
 
 
I/O Register bits:                  0
I/O Register bits:                  0
Register bits not including I/Os:   1312 (2%)
Register bits not including I/Os:   1630 (2%)
 
 
Global Clock Buffers: 1 of 32 (3%)
Global Clock Buffers: 1 of 32 (3%)
 
 
Total load per clock:
Total load per clock:
   fpu_mul|clk: 1349
   fpu_mul|clk: 1722
 
 
Mapping Summary:
Mapping Summary:
Total  LUTs: 364 (0%)
Total  LUTs: 643 (1%)
Total  LUTs: 643 (1%)
Total  LUTs: 643 (1%)

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