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[/] [dp_pkg/] [trunk/] [dp_stream_stimuli.vhd] - Diff between revs 2 and 5

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Rev 2 Rev 5
Line 60... Line 60... 
    g_channel_incr   : NATURAL := 1;    -- when 0 keep fixed at init value, when 1 increment at every sop
 
    g_channel_incr   : NATURAL := 1;    -- when 0 keep fixed at init value, when 1 increment at every sop
 
    -- specific
 
    -- specific
 
    g_in_dat_w       : NATURAL := 32;
 
    g_in_dat_w       : NATURAL := 32;
 
    g_nof_repeat     : NATURAL := 5;
 
    g_nof_repeat     : NATURAL := 5;
 
    g_pkt_len        : NATURAL := 16;
 
    g_pkt_len        : NATURAL := 16;
 
    g_pkt_gap        : NATURAL := 4
 
    g_pkt_gap        : NATURAL := 4;
 
 
 
    g_wait_last_evt  : NATURAL := 100   -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
 
  );
 
  );
 
  PORT (
 
  PORT (
 
    rst               : IN  STD_LOGIC;
 
    rst               : IN  STD_LOGIC;
 
    clk               : IN  STD_LOGIC;
 
    clk               : IN  STD_LOGIC;
 
 
 
 
Line 166... Line 167... 
    v_last.data    := INCR_UVEC(v_sosi.data, g_pkt_len-1);
 
    v_last.data    := INCR_UVEC(v_sosi.data, g_pkt_len-1);
 
    v_last.data    := RESIZE_DP_DATA(v_last.data(g_in_dat_w-1 DOWNTO 0));  -- wrap when >= 2**g_in_dat_w
 
    v_last.data    := RESIZE_DP_DATA(v_last.data(g_in_dat_w-1 DOWNTO 0));  -- wrap when >= 2**g_in_dat_w
 
    last_snk_in <= v_last;
 
    last_snk_in <= v_last;
 
 
 
 
 
    -- Signal end of stimuli
 
    -- Signal end of stimuli
 
    proc_common_wait_some_cycles(clk, 100);  -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
 
    proc_common_wait_some_cycles(clk, g_wait_last_evt);  -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
 
    proc_common_gen_pulse(clk, last_snk_in_evt);
 
    proc_common_gen_pulse(clk, last_snk_in_evt);
 
    proc_common_wait_some_cycles(clk, 50);
 
    proc_common_wait_some_cycles(clk, 50);
 
    tb_end <= '1';
 
    tb_end <= '1';
 
    WAIT;
 
    WAIT;
 
  END PROCESS;
 
  END PROCESS;

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