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library ieee;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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entity e1_frm is
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port(E1_out,nr: out STD_LOGIC;--output serial stream
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E1_CLK_in: in STD_LOGIC;--clock for output stream
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reset: in STD_LOGIC; -- reset
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frame_start,RD: out STD_LOGIC;-- determines frame start, RD - read signal for "look forvard" memory
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data: in STD_LOGIC_VECTOR (0 to 7);
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zero_frame: in STD_LOGIC_VECTOR (0 to 7)-- zero frame data
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--isEmpty : in STD_LOGIC
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);
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end e1_frm;
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architecture BEHAVIOR of e1_frm is
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SIGNAL cnt: integer range 0 to 7;
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signal ires,state,frame_type: STD_LOGIC;
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signal iData: STD_LOGIC_VECTOR (0 to 7);
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begin
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nr<=ires;
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------------------------------------------------------------------------------------------------------
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-- lower bits come first!!!
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-- parallel to serial converter
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------------------------------------------------------------------------------------------------------
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process (E1_CLK_in,ires)
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begin
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if (ires='1') then
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cnt<=0;
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E1_out<='0';
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elsif (FALLING_EDGE(E1_CLK_in)) then
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E1_out<=iData(cnt);
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cnt<=cnt+1;
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end if;
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end process;
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--------------------------------------------------------------------------------------------------------
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--this trigger is used to eliminate "short reset" situation: when reset becomes low during "high" E1_CLK_in
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--in this situation transmitter starts before state machine set up valid iData signal
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--------------------------------------------------------------------------------------------------------
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process (E1_CLK_in,reset)
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begin
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if (reset='1') then
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ires<='1';
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elsif (FALLING_EDGE(E1_CLK_in)) then
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ires<='0';
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end if;
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end process;
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--------------------------------------------------------------------------------------------------------
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-- state machine
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-- 0 - zero time slot generation.
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-- 1 - transmission
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--------------------------------------------------------------------------------------------------------
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process (E1_CLK_in,ires)
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variable byte_cnt: integer range 0 to 31;
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begin
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if (ires='1') then
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state<='0';
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frame_type<='0';
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elsif (RISING_EDGE(E1_CLK_in)) then
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CASE state IS
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WHEN '0' =>
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byte_cnt:=0;
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frame_start<='1';
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if(frame_type='0') then
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iData<="10011011";
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else
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iData(0)<=zero_frame(0);
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iData(2 to 7)<=zero_frame(2 to 7);
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iData(1)<='1';--warranty of correct frame signal
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end if;
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state<=CONV_STD_LOGIC_VECTOR(cnt,3)(0) and CONV_STD_LOGIC_VECTOR(cnt,3)(1) and CONV_STD_LOGIC_VECTOR(cnt,3)(2);
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WHEN '1' =>
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frame_start<='0';
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if (cnt = 0) then
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iData<=data;
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RD<='1';
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else
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RD<='0';
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end if;
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if(cnt=7)then
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if(byte_cnt=30) then
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state<='0';-- frame trensmitted
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frame_type<=not(frame_type);
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else
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byte_cnt:=byte_cnt+1;
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end if;
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end if;
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when others=> state<='0';
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END CASE;
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end if;
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end process;
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end BEHAVIOR;
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