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Line 31... |
output reg done;
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output reg done;
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output reg [`WIDTH:0] x3, y3;
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output reg [`WIDTH:0] x3, y3;
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output reg zero3;
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output reg zero3;
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reg [`WIDTH:0] x2, y2; reg zero2; // the result
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reg [`WIDTH:0] x2, y2; reg zero2; // the result
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wire [`WIDTH:0] x4, y4; wire zero4;
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reg [`WIDTH:0] x4, y4; wire zero4;
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wire [`WIDTH:0] x5, y5; wire zero5;
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wire [`WIDTH:0] x5, y5; wire zero5;
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reg [`SCALAR_WIDTH : 0] k; // the scalar value
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reg [`SCALAR_WIDTH : 0] k; // the scalar value
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reg [`SCALAR_WIDTH+1 : 0] i; // the counter
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reg [`SCALAR_WIDTH+1 : 0] i; // the counter
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reg op;
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reg op;
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wire p, p2, rst, done1;
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wire p, p2, rst, done1;
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assign x4 = (~op) ? x2 : (k[`SCALAR_WIDTH]?x1:0);
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assign y4 = (~op) ? y2 : (k[`SCALAR_WIDTH]?y1:0);
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assign zero4 = (~op) ? zero2 : (k[`SCALAR_WIDTH]?zero1:1);
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assign zero4 = (~op) ? zero2 : (k[`SCALAR_WIDTH]?zero1:1);
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assign rst = reset | p2 ;
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assign rst = reset | p2 ;
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point_add
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point_add
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ins1 (clk, rst, x2, y2, zero2, x4, y4, zero4, done1, x5, y5, zero5);
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ins1 (clk, rst, x2, y2, zero2, x4, y4, zero4, done1, x5, y5, zero5);
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func6
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func6
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ins2 (clk, reset, done1, p),
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ins2 (clk, reset, done1, p),
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ins3 (clk, reset, p, p2);
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ins3 (clk, reset, p, p2);
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) begin x4 <= 0; y4 <= 0; end
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else
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begin
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x4 <= (~op) ? x2 : (k[`SCALAR_WIDTH]?x1:0);
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y4 <= (~op) ? y2 : (k[`SCALAR_WIDTH]?y1:0);
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end
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always @ (posedge clk)
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if (reset) i <= 1;
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if (reset) i <= 1;
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else if ((op & p) | i[`SCALAR_WIDTH+1]) i <= i << 1;
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else if ((op & p) | i[`SCALAR_WIDTH+1]) i <= i << 1;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) k <= c;
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if (reset) k <= c;
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