Line 31... |
Line 31... |
output reg done;
|
output reg done;
|
output reg [`WIDTH:0] x3, y3;
|
output reg [`WIDTH:0] x3, y3;
|
output reg zero3;
|
output reg zero3;
|
|
|
reg [`WIDTH:0] x2, y2; reg zero2; // the result
|
reg [`WIDTH:0] x2, y2; reg zero2; // the result
|
wire [`WIDTH:0] x4, y4; wire zero4;
|
reg [`WIDTH:0] x4, y4; wire zero4;
|
wire [`WIDTH:0] x5, y5; wire zero5;
|
wire [`WIDTH:0] x5, y5; wire zero5;
|
reg [`SCALAR_WIDTH : 0] k; // the scalar value
|
reg [`SCALAR_WIDTH : 0] k; // the scalar value
|
reg [`SCALAR_WIDTH+1 : 0] i; // the counter
|
reg [`SCALAR_WIDTH+1 : 0] i; // the counter
|
reg op;
|
reg op;
|
wire p, p2, rst, done1;
|
wire p, p2, rst, done1;
|
|
|
assign x4 = (~op) ? x2 : (k[`SCALAR_WIDTH]?x1:0);
|
|
assign y4 = (~op) ? y2 : (k[`SCALAR_WIDTH]?y1:0);
|
|
assign zero4 = (~op) ? zero2 : (k[`SCALAR_WIDTH]?zero1:1);
|
assign zero4 = (~op) ? zero2 : (k[`SCALAR_WIDTH]?zero1:1);
|
assign rst = reset | p2 ;
|
assign rst = reset | p2 ;
|
|
|
point_add
|
point_add
|
ins1 (clk, rst, x2, y2, zero2, x4, y4, zero4, done1, x5, y5, zero5);
|
ins1 (clk, rst, x2, y2, zero2, x4, y4, zero4, done1, x5, y5, zero5);
|
func6
|
func6
|
ins2 (clk, reset, done1, p),
|
ins2 (clk, reset, done1, p),
|
ins3 (clk, reset, p, p2);
|
ins3 (clk, reset, p, p2);
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
|
if (reset) begin x4 <= 0; y4 <= 0; end
|
|
else
|
|
begin
|
|
x4 <= (~op) ? x2 : (k[`SCALAR_WIDTH]?x1:0);
|
|
y4 <= (~op) ? y2 : (k[`SCALAR_WIDTH]?y1:0);
|
|
end
|
|
|
|
always @ (posedge clk)
|
if (reset) i <= 1;
|
if (reset) i <= 1;
|
else if ((op & p) | i[`SCALAR_WIDTH+1]) i <= i << 1;
|
else if ((op & p) | i[`SCALAR_WIDTH+1]) i <= i << 1;
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset) k <= c;
|
if (reset) k <= c;
|