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module busctrl(cpu_en, cpu_wr, cpu_size, cpu_addr, cpu_data_out, cpu_data_in, cpu_wt,
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//
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ram_en, ram_wr, ram_size, ram_addr, ram_data_in, ram_data_out, ram_wt,
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// busctrl.v -- bus controller
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rom_en, rom_wr, rom_size, rom_addr, rom_data_out, rom_wt,
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//
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tmr_en, tmr_wr, tmr_addr2, tmr_data_in, tmr_data_out, tmr_wt,
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dsp_en, dsp_wr, dsp_addr, dsp_data_in, dsp_data_out, dsp_wt,
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module busctrl(cpu_en, cpu_wr, cpu_size, cpu_addr,
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kbd_en, kbd_wr, kbd_addr2, kbd_data_in, kbd_data_out, kbd_wt,
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cpu_data_out, cpu_data_in, cpu_wt,
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ser0_en, ser0_wr, ser0_addr, ser0_data_in, ser0_data_out, ser0_wt,
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ram_en, ram_wr, ram_size, ram_addr,
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ser1_en, ser1_wr, ser1_addr, ser1_data_in, ser1_data_out, ser1_wt,
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ram_data_in, ram_data_out, ram_wt,
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dsk_en, dsk_wr, dsk_addr, dsk_data_in, dsk_data_out, dsk_wt);
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rom_en, rom_wr, rom_size, rom_addr,
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rom_data_out, rom_wt,
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tmr_en, tmr_wr, tmr_addr,
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tmr_data_in, tmr_data_out, tmr_wt,
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dsp_en, dsp_wr, dsp_addr,
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dsp_data_in, dsp_data_out, dsp_wt,
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kbd_en, kbd_wr, kbd_addr,
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kbd_data_in, kbd_data_out, kbd_wt,
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ser0_en, ser0_wr, ser0_addr,
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ser0_data_in, ser0_data_out, ser0_wt,
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ser1_en, ser1_wr, ser1_addr,
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ser1_data_in, ser1_data_out, ser1_wt,
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dsk_en, dsk_wr, dsk_addr,
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dsk_data_in, dsk_data_out, dsk_wt);
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// cpu
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// cpu
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input cpu_en;
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input cpu_en;
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input cpu_wr;
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input cpu_wr;
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input [1:0] cpu_size;
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input [1:0] cpu_size;
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input [31:0] cpu_addr;
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input [31:0] cpu_addr;
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input [31:0] rom_data_out;
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input [31:0] rom_data_out;
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input rom_wt;
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input rom_wt;
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// tmr
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// tmr
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output tmr_en;
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output tmr_en;
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output tmr_wr;
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output tmr_wr;
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output tmr_addr2;
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output tmr_addr;
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output [31:0] tmr_data_in;
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output [31:0] tmr_data_in;
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input [31:0] tmr_data_out;
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input [31:0] tmr_data_out;
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input tmr_wt;
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input tmr_wt;
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// dsp
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// dsp
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output dsp_en;
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output dsp_en;
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input [15:0] dsp_data_out;
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input [15:0] dsp_data_out;
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input dsp_wt;
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input dsp_wt;
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// kbd
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// kbd
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output kbd_en;
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output kbd_en;
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output kbd_wr;
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output kbd_wr;
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output kbd_addr2;
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output kbd_addr;
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output [7:0] kbd_data_in;
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output [7:0] kbd_data_in;
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input [7:0] kbd_data_out;
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input [7:0] kbd_data_out;
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input kbd_wt;
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input kbd_wt;
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// ser0
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// ser0
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output ser0_en;
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output ser0_en;
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input [31:0] dsk_data_out;
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input [31:0] dsk_data_out;
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input dsk_wt;
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input dsk_wt;
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wire i_o_en;
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wire i_o_en;
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// decoder
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//
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// address decoder
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//
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// RAM: architectural limit = 512 MB
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// board limit = 32 MB
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assign ram_en =
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assign ram_en =
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(cpu_en == 1 && cpu_addr[31:29] == 3'b000
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(cpu_en == 1 && cpu_addr[31:29] == 3'b000
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&& cpu_addr[28:25] == 4'b0000) ? 1 : 0;
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&& cpu_addr[28:25] == 4'b0000) ? 1 : 0;
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// ROM: architectural limit = 256 MB
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// board limit = 2 MB
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assign rom_en =
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assign rom_en =
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(cpu_en == 1 && cpu_addr[31:28] == 4'b0010
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(cpu_en == 1 && cpu_addr[31:28] == 4'b0010
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&& cpu_addr[27:21] == 7'b0000000) ? 1 : 0;
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&& cpu_addr[27:21] == 7'b0000000) ? 1 : 0;
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// I/O: architectural limit = 256 MB
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assign i_o_en =
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assign i_o_en =
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(cpu_en == 1 && cpu_addr[31:28] == 4'b0011) ? 1 : 0;
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(cpu_en == 1 && cpu_addr[31:28] == 4'b0011) ? 1 : 0;
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assign tmr_en =
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assign tmr_en =
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(i_o_en == 1 && cpu_addr[27:20] == 8'h00) ? 1 : 0;
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(i_o_en == 1 && cpu_addr[27:20] == 8'h00) ? 1 : 0;
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assign dsp_en =
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assign dsp_en =
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(i_o_en == 1 && cpu_addr[27:20] == 8'h01) ? 1 : 0;
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(i_o_en == 1 && cpu_addr[27:20] == 8'h01) ? 1 : 0;
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assign kbd_en =
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assign kbd_en =
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(i_o_en == 1 && cpu_addr[27:20] == 8'h02) ? 1 : 0;
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(i_o_en == 1 && cpu_addr[27:20] == 8'h02) ? 1 : 0;
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assign ser0_en =
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assign ser0_en =
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(i_o_en == 1 && cpu_addr[27:20] == 8'h03
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(i_o_en == 1 && cpu_addr[27:20] == 8'h03
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&& cpu_addr[ 5: 4] == 2'b00) ? 1 : 0;
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&& cpu_addr[19:12] == 8'h00) ? 1 : 0;
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assign ser1_en =
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assign ser1_en =
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(i_o_en == 1 && cpu_addr[27:20] == 8'h03
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(i_o_en == 1 && cpu_addr[27:20] == 8'h03
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&& cpu_addr[ 5: 4] == 2'b01) ? 1 : 0;
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&& cpu_addr[19:12] == 8'h01) ? 1 : 0;
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assign dsk_en =
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assign dsk_en =
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(i_o_en == 1 && cpu_addr[27:20] == 8'h04) ? 1 : 0;
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(i_o_en == 1 && cpu_addr[27:20] == 8'h04) ? 1 : 0;
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// to cpu
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// to cpu
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assign cpu_wt =
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assign cpu_wt =
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assign rom_size[1:0] = cpu_size[1:0];
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assign rom_size[1:0] = cpu_size[1:0];
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assign rom_addr[20:0] = cpu_addr[20:0];
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assign rom_addr[20:0] = cpu_addr[20:0];
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// to tmr
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// to tmr
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assign tmr_wr = cpu_wr;
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assign tmr_wr = cpu_wr;
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assign tmr_addr2 = cpu_addr[2];
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assign tmr_addr = cpu_addr[2];
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assign tmr_data_in[31:0] = cpu_data_out[31:0];
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assign tmr_data_in[31:0] = cpu_data_out[31:0];
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// to dsp
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// to dsp
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assign dsp_wr = cpu_wr;
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assign dsp_wr = cpu_wr;
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assign dsp_addr[13:2] = cpu_addr[13:2];
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assign dsp_addr[13:2] = cpu_addr[13:2];
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assign dsp_data_in[15:0] = cpu_data_out[15:0];
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assign dsp_data_in[15:0] = cpu_data_out[15:0];
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// to kbd
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// to kbd
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assign kbd_wr = cpu_wr;
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assign kbd_wr = cpu_wr;
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assign kbd_addr2 = cpu_addr[2];
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assign kbd_addr = cpu_addr[2];
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assign kbd_data_in[7:0] = cpu_data_out[7:0];
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assign kbd_data_in[7:0] = cpu_data_out[7:0];
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// to ser0
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// to ser0
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assign ser0_wr = cpu_wr;
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assign ser0_wr = cpu_wr;
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assign ser0_addr[3:2] = cpu_addr[3:2];
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assign ser0_addr[3:2] = cpu_addr[3:2];
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