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//
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// dsp.v -- character display interface
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//
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module dsp(clk, reset,
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module dsp(clk, reset,
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addr, en, wr, wt,
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addr, en, wr, wt,
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data_in, data_out,
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data_in, data_out,
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hsync, vsync,
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hsync, vsync,
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r, g, b);
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r, g, b);
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// internal interface
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input clk;
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input clk;
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input reset;
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input reset;
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input [13:2] addr;
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input [13:2] addr;
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input en;
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input en;
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input wr;
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input wr;
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output wt;
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output wt;
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input [15:0] data_in;
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input [15:0] data_in;
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output [15:0] data_out;
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output [15:0] data_out;
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// external interface
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output hsync;
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output hsync;
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output vsync;
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output vsync;
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output [2:0] r;
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output [2:0] r;
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output [2:0] g;
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output [2:0] g;
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output [2:0] b;
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output [2:0] b;
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reg state;
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reg state;
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display display1 (.clk(clk),
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display display1(
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.clk(clk),
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.dsp_row(addr[13:9]),
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.dsp_row(addr[13:9]),
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.dsp_col(addr[8:2]),
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.dsp_col(addr[8:2]),
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.dsp_en(en),
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.dsp_en(en),
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.dsp_wr(wr),
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.dsp_wr(wr),
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.dsp_wr_data(data_in[15:0]),
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.dsp_wr_data(data_in[15:0]),
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.dsp_rd_data(data_out[15:0]),
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.dsp_rd_data(data_out[15:0]),
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.hsync(hsync),
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.hsync(hsync),
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.vsync(vsync),
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.vsync(vsync),
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.r(r[2:0]),
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.r(r[2:0]),
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.g(g[2:0]),
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.g(g[2:0]),
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.b(b[2:0]));
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.b(b[2:0])
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);
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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if (reset == 1) begin
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state <= 1'b0;
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state <= 1'b0;
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end else begin
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end else begin
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