| Line 133... |
Line 133... |
wire rom_wr;
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wire rom_wr;
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wire [1:0] rom_size;
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wire [1:0] rom_size;
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wire [20:0] rom_addr;
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wire [20:0] rom_addr;
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wire [31:0] rom_data_out;
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wire [31:0] rom_data_out;
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wire rom_wt;
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wire rom_wt;
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// tmr
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// tmr0
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wire tmr_en;
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wire tmr0_en;
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wire tmr_wr;
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wire tmr0_wr;
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wire [3:2] tmr_addr;
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wire [3:2] tmr0_addr;
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wire [31:0] tmr_data_in;
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wire [31:0] tmr0_data_in;
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wire [31:0] tmr_data_out;
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wire [31:0] tmr0_data_out;
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wire tmr_wt;
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wire tmr0_wt;
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wire tmr_irq;
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wire tmr0_irq;
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// tmr1
|
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wire tmr1_en;
|
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wire tmr1_wr;
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wire [3:2] tmr1_addr;
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wire [31:0] tmr1_data_in;
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wire [31:0] tmr1_data_out;
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wire tmr1_wt;
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wire tmr1_irq;
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// dsp
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// dsp
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wire dsp_en;
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wire dsp_en;
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wire dsp_wr;
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wire dsp_wr;
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wire [13:2] dsp_addr;
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wire [13:2] dsp_addr;
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wire [15:0] dsp_data_in;
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wire [15:0] dsp_data_in;
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| Line 217... |
Line 225... |
.rom_wr(rom_wr),
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.rom_wr(rom_wr),
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.rom_size(rom_size[1:0]),
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.rom_size(rom_size[1:0]),
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.rom_addr(rom_addr[20:0]),
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.rom_addr(rom_addr[20:0]),
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.rom_data_out(rom_data_out[31:0]),
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.rom_data_out(rom_data_out[31:0]),
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.rom_wt(rom_wt),
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.rom_wt(rom_wt),
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// tmr
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// tmr0
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.tmr_en(tmr_en),
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.tmr0_en(tmr0_en),
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.tmr_wr(tmr_wr),
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.tmr0_wr(tmr0_wr),
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.tmr_addr(tmr_addr[3:2]),
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.tmr0_addr(tmr0_addr[3:2]),
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.tmr_data_in(tmr_data_in[31:0]),
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.tmr0_data_in(tmr0_data_in[31:0]),
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.tmr_data_out(tmr_data_out[31:0]),
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.tmr0_data_out(tmr0_data_out[31:0]),
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.tmr_wt(tmr_wt),
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.tmr0_wt(tmr0_wt),
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// tmr1
|
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.tmr1_en(tmr1_en),
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.tmr1_wr(tmr1_wr),
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.tmr1_addr(tmr1_addr[3:2]),
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.tmr1_data_in(tmr1_data_in[31:0]),
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.tmr1_data_out(tmr1_data_out[31:0]),
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.tmr1_wt(tmr1_wt),
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// dsp
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// dsp
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.dsp_en(dsp_en),
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.dsp_en(dsp_en),
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.dsp_wr(dsp_wr),
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.dsp_wr(dsp_wr),
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.dsp_addr(dsp_addr[13:2]),
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.dsp_addr(dsp_addr[13:2]),
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.dsp_data_in(dsp_data_in[15:0]),
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.dsp_data_in(dsp_data_in[15:0]),
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| Line 274... |
Line 289... |
.bus_data_out(cpu_data_out[31:0]),
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.bus_data_out(cpu_data_out[31:0]),
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.bus_wt(cpu_wt),
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.bus_wt(cpu_wt),
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.irq(cpu_irq[15:0])
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.irq(cpu_irq[15:0])
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);
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);
|
|
|
assign cpu_irq[15] = 1'b0;
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assign cpu_irq[15] = tmr1_irq;
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assign cpu_irq[14] = tmr_irq;
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assign cpu_irq[14] = tmr0_irq;
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assign cpu_irq[13] = 1'b0;
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assign cpu_irq[13] = 1'b0;
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assign cpu_irq[12] = 1'b0;
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assign cpu_irq[12] = 1'b0;
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assign cpu_irq[11] = 1'b0;
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assign cpu_irq[11] = 1'b0;
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assign cpu_irq[10] = 1'b0;
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assign cpu_irq[10] = 1'b0;
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assign cpu_irq[ 9] = 1'b0;
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assign cpu_irq[ 9] = 1'b0;
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| Line 332... |
Line 347... |
.byte_n(flash_byte_n),
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.byte_n(flash_byte_n),
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.a(flash_a[19:0]),
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.a(flash_a[19:0]),
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.d(flash_d[15:0])
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.d(flash_d[15:0])
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);
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);
|
|
|
tmr tmr1(
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tmr tmr1_0(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.en(tmr_en),
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.en(tmr0_en),
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.wr(tmr_wr),
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.wr(tmr0_wr),
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.addr(tmr_addr[3:2]),
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.addr(tmr0_addr[3:2]),
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.data_in(tmr_data_in[31:0]),
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.data_in(tmr0_data_in[31:0]),
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.data_out(tmr_data_out[31:0]),
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.data_out(tmr0_data_out[31:0]),
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.wt(tmr_wt),
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.wt(tmr0_wt),
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.irq(tmr_irq)
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.irq(tmr0_irq)
|
|
);
|
|
|
|
tmr tmr1_1(
|
|
.clk(clk),
|
|
.reset(reset),
|
|
.en(tmr1_en),
|
|
.wr(tmr1_wr),
|
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.addr(tmr1_addr[3:2]),
|
|
.data_in(tmr1_data_in[31:0]),
|
|
.data_out(tmr1_data_out[31:0]),
|
|
.wt(tmr1_wt),
|
|
.irq(tmr1_irq)
|
);
|
);
|
|
|
dsp dsp1(
|
dsp dsp1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
