URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [tags/] [eco32-0.24/] [fpga/] [xsa-xst-3/] [eco32.ucf] - Diff between revs 30 and 67

Rev 30	Rev 67
Line 1...	Line 1...
`#PACE: Start of Constraints generated by PACE`	`#`
	`# eco32.ucf -- ECO32 user constraints for XSA-3S1000 + XST-3 board`
	`#`

`#PACE: Start of PACE I/O Pin Assignments`
`NET "ata_cs0_n" LOC = "g15" ;`	`NET "ata_cs0_n" LOC = "g15" ;`
`NET "ata_cs1_n" LOC = "g14" ;`	`NET "ata_cs1_n" LOC = "g14" ;`
`NET "ata_dmack_n" LOC = "k1" ;`	`NET "ata_dmack_n" LOC = "k1" ;`
`NET "ata_dmarq" LOC = "l4" ;`	`NET "ata_dmarq" LOC = "l4" ;`
`NET "ata_intrq" LOC = "h15" ;`	`NET "ata_intrq" LOC = "h15" ;`
Line 131...	Line 132...
`NET "sdram_udqm" LOC = "d9" ;`	`NET "sdram_udqm" LOC = "d9" ;`
`NET "sdram_we_n" LOC = "b10" ;`	`NET "sdram_we_n" LOC = "b10" ;`
`NET "slot1_cs_n" LOC = "e15" ;`	`NET "slot1_cs_n" LOC = "e15" ;`
`NET "slot2_cs_n" LOC = "d16" ;`	`NET "slot2_cs_n" LOC = "d16" ;`
`NET "vsync" LOC = "d8" ;`	`NET "vsync" LOC = "d8" ;`

`#PACE: Start of PACE Area Constraints`

`#PACE: Start of PACE Prohibit Constraints`

`#PACE: End of Constraints generated by PACE`