| Line 35... |
Line 35... |
reg ata_out_muxctrl;
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reg ata_out_muxctrl;
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assign internal_bus_addr[9:0] = bus_addr[11:2];
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assign internal_bus_addr[9:0] = bus_addr[11:2];
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assign internal_ata_addr[9:0] = ata_addr[11:2];
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assign internal_ata_addr[9:0] = ata_addr[11:2];
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assign lo_din_bus = bus_din[15:0];
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assign lo_din_bus = { bus_din[7:0], bus_din[15:8] };
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assign hi_din_bus = bus_din[31:16];
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assign hi_din_bus = { bus_din[23:16], bus_din[31:24] };
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assign lo_din_ata = ata_din;
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assign lo_din_ata = ata_din;
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assign hi_din_ata = ata_din;
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assign hi_din_ata = ata_din;
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// pipeline register for ata output mux control
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// pipeline register for ata output mux control
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always @(posedge clk) begin
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always @(posedge clk) begin
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ata_out_muxctrl <= ata_addr[1];
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ata_out_muxctrl <= ata_addr[1];
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end
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end
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assign bus_dout = { hi_dout_bus, lo_dout_bus };
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assign bus_dout = { hi_dout_bus[7:0], hi_dout_bus[15:8],
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lo_dout_bus[7:0], lo_dout_bus[15:8] };
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assign ata_dout = ata_out_muxctrl ? lo_dout_ata : hi_dout_ata;
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assign ata_dout = ata_out_muxctrl ? lo_dout_ata : hi_dout_ata;
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assign lo_write_bus = bus_write;
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assign lo_write_bus = bus_write;
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assign hi_write_bus = bus_write;
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assign hi_write_bus = bus_write;
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assign lo_write_ata = ata_write & ata_addr[1];
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assign lo_write_ata = ata_write & ata_addr[1];
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