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https://opencores.org/ocsvn/eco32/eco32/trunk
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| Rev 27 |
Rev 67 |
| Line 1... |
Line 1... |
module tmr(clk, reset,
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module tmr(clk, reset,
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en, wr, addr2,
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en, wr, addr,
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data_in, data_out,
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data_in, data_out,
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wt, irq);
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wt, irq);
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input clk;
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input clk;
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input reset;
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input reset;
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input en;
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input en;
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input wr;
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input wr;
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input addr2;
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input addr;
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input [31:0] data_in;
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input [31:0] data_in;
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output [31:0] data_out;
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output [31:0] data_out;
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output wt;
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output wt;
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output irq;
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output irq;
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Line 63... |
ien <= 0;
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ien <= 0;
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end else begin
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end else begin
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if (expired == 1) begin
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if (expired == 1) begin
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alarm <= 1;
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alarm <= 1;
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end else begin
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end else begin
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if (en == 1 && wr == 1 && addr2 == 0) begin
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if (en == 1 && wr == 1 && addr == 0) begin
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alarm <= data_in[0];
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alarm <= data_in[0];
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ien <= data_in[1];
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ien <= data_in[1];
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end
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end
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if (en == 1 && wr == 1 && addr2 == 1) begin
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if (en == 1 && wr == 1 && addr == 1) begin
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divisor <= data_in;
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divisor <= data_in;
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divisor_loaded <= 1;
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divisor_loaded <= 1;
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end else begin
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end else begin
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divisor_loaded <= 0;
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divisor_loaded <= 0;
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end
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end
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end
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end
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end
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end
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end
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end
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assign data_out =
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assign data_out =
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(addr2 == 0) ? { 28'h0000000, 2'b00, ien, alarm } :
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(addr == 0) ? { 28'h0000000, 2'b00, ien, alarm } :
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divisor;
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divisor;
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assign wt = 0;
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assign wt = 0;
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assign irq = ien & alarm;
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assign irq = ien & alarm;
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endmodule
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endmodule
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