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03-Feb-2014
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03-Feb-2014
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Project "ECO32" created on OpenCores, based on version eco32-0.22:
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Project "ECO32" created on OpenCores, based on version eco32-0.22:
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http://opencores.org/project,eco32
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http://opencores.org/project,eco32
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04-Feb-2014
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Main Makefile, lcc, docs, binutils, sim, and simtest added.
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05-Feb-2014
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FPGA implementations, hwtests, monitor, disk and standalone
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programs added.
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07-Feb-2014
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Release eco32-0.22 tagged.
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08-Feb-2014
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ECO32 manual added. It can now be generated from TeX sources.
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18-Feb-2014
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18-Feb-2014
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Several changes in the simulator:
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Several changes in the simulator:
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a) There are two independent identical timer/counters
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a) There are two independent identical timer/counters
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available, of course with different interrupts and I/O
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available, of course with different interrupts and I/O
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addresses (see below).
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addresses (see below).
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b) The timer/counters are readable, so that they can
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b) The timer/counters are readable, so that they can
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be used for short-time measurements. They count clock
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be used for short-time measurements. They count clock
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cycles (no pre-scaling any longer). This change will
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cycles (no pre-scaling any longer). This change will
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affect all programs which use the timer/counters.
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affect all programs which use the timer/counters.
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c) The simulation timing model is completely based on
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c) The simulation timing model is completely based on
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clock cycles (and does no longer try to function in
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clock cycles (and does no longer tries to function in
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some sort of "real-time"). As there is no real clock
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some sort of "real-time"). As there is no real clock
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within the simulator, but the natural time unit is
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within the simulator, but the natural time unit is
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one instruction, the simulation time is incremented
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one instruction, the simulation time is incremented
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by the CPI value (clock cycles per instruction) every
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by the CPI value (clock cycles per instruction) every
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instruction. I measured the CPI value in the real ECO32
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instruction. I measured the CPI value in the real ECO32
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programs which use more than one terminal.
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programs which use more than one terminal.
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f) The ECO32 simulation got a new peripheral, called the
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f) The ECO32 simulation got a new peripheral, called the
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"shutdown device". A write to address 0xFF100000 results
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"shutdown device". A write to address 0xFF100000 results
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in terminating the simulation run, with the lower 8 bits
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in terminating the simulation run, with the lower 8 bits
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of the data written supplied as exit status.
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of the data written supplied as exit status.
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19-Feb-2014
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In the hardware section, only the latest FPGA implementation
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was kept.
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20-Feb-2014
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New ISE project file created. In the LCC section, lburg/gram.c
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gets re-generated from the grammar file. Two new simulator
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tests written. Standalone programs updated.
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22-Feb-2014
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Tools: bin2exo tool updated, bin2mcs tool added. Hardware:
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character generator generator added, display memory generator
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added. Monitor: load server added. Disk: disk server renamed
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and updated.
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23-Feb-2014
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Monitor directories re-structured. Monitors extensively updated.
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FPGA implementation updated; timer is now equal to port-15.
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24-Feb-2014
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Hardware: timer counts clock cycles, counter is readable, two
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timers are now available.
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25-Feb-2014
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Simulator: IRQ 15 explanation added, IRQ 0-3 explanations
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changed.
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26-Feb-2014
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Hardware: cpu is now equal to port-15. Constraints file for
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XESS board re-formatted.
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27-Feb-2014
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Simulator: tlbBadAddr register is now called mmuBadAddr.
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28-Feb-2014
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Hardware tests (kbdtest): second timer added.
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01-Mar-2014
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Hardware tests (xcptest): test the bad address register too.
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Hardware: cpu now also has a bad address register.
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*****************************************************************
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Stefan Kristiansson's Linux port to ECO32 is running on the FPGA!
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*****************************************************************
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Simulator: change command @ -> #, better help for commands.
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Simulator: individual help messages corrected.
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02-Mar-2014
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Monitor: bad address register added.
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Monitor: bootstrap parameters modified.
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Disk: master boot made compatible with monitor.
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03-Mar-2014
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DE0-Nano board arrived. I can download a simple design.
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04-Mar-2014
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The Nano board does only have a bit-serial ROM. Besides the
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configuration bitstring for the FPGA there is enough room in
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it to store the machine monitor, but this program cannot
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reasonably be executed from there. So it must be copied to
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RAM before it can be started. This is also the case with the
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S3E starter kit board - this board indeed does have a parallel
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ROM but alas, it must be disabled in order to use the A/D or
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D/A converters. Therefore it is best to run the monitor from
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RAM in any case. Consequences: the boot procedures must again
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be revised.
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Monitor: do not set sp on bootstrap.
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EOS32 bootstrap update.
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05-Mar-2014
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Simulator: -a command line option added (which specifies a load
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address where a binary file is loaded when -l is given).
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Compiler: -Wo-kernel relocates code to 0xC0010000.
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06-Mar-2014
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Standalone programs (hello, hello2, memsize, onetask, twotasks-1,
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twotasks-2) executable at 0xC0010000.
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07-Mar-2014
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Standalone programs (wrtmbr, dskchk) executable at 0xC0010000.
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08-Mar-2014
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Standalone programs (shpart, mkpart) executable at 0xC0010000.
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Verified the four ways that a standalone program can be executed:
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- simulator and -l/-a command line options
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- simulator and simulated disk (boot the standalone program)
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- FPGA and load server (load the standalone program)
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- FPGA and simulated disk (boot the standalone program)
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