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Here are two implementations of a memory controller, intended
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Here are two implementations of a memory controller, intended
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to be used on a real FPGA. The names of the subdirectories are
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to be used on a real FPGA. The names of the subdirectories are
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the same as the corresponding ones in ../sim. memctrl-0 does
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the same as the corresponding ones in ../sim. memctrl-0 does
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not exist here, because the underlying RAM model cannot be
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not exist here, because its underlying RAM model cannot be
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synthesized on the real FPGA. memctrl-1 is a memory controller
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synthesized on the real FPGA. memctrl-1 is a memory controller
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for SDRAM running at 100 MHz, where test circuit uses the same
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for SDRAM running at 100 MHz, where the test circuit uses the
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clock rate. memctrl-2 is very similar to this, but runs the
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same clock rate. memctrl-2 is very similar to this, but runs
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test circuit at 50 MHz. For details see the README files in
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the test circuit at 50 MHz. For details see the README files
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the corresponding subdirectories of ../sim.
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in the corresponding subdirectories of ../sim.
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in the corresponding subdirectories of ../sim.
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in the corresponding subdirectories of ../sim.
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