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https://opencores.org/ocsvn/eco32/eco32/trunk
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| Rev 297 |
Rev 300 |
| Line 53... |
Line 53... |
counter[3:0] <= 4'h0;
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counter[3:0] <= 4'h0;
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end else begin
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end else begin
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if (counter[3:0] == 4'h0) begin
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if (counter[3:0] == 4'h0) begin
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if (stb & ~we) begin
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if (stb & ~we) begin
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// a read may need some clock cycles
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// a read may need some clock cycles
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counter <= `RD_CYCLES - 1;
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counter[3:0] <= `RD_CYCLES - 1;
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end
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end
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if (stb & we) begin
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if (stb & we) begin
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// a write may need some clock cycles
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// a write may need some clock cycles
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counter <= `WR_CYCLES - 1;
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counter[3:0] <= `WR_CYCLES - 1;
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end
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end
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end else begin
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end else begin
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counter[3:0] <= counter[3:0] - 1;
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counter[3:0] <= counter[3:0] - 1;
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end
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end
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end
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end
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