?rev1line? |
?rev2line? |
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Purpose
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-------
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This test circuit allows speed measurements of the old
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memory controller (written by Dave Vanden Bout), driving
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the on-board SDRAM of the XESS board. To do timing
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measurements of reads or writes, wire the "we" signal
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to 0 or 1, respectively. It is also possible to get a
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mix of reads and writes if the "we" signal is a function
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of (some bits of) the counter "count". Note that only
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32-bit accesses are performed. The clock rate is 50 MHz.
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Read
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----
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41.8 s
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41.9 s
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41.7 s
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average:
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41.8 s / 2^27 read cycles = 311.4 ns / read cycle
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which means 15.6 clock cycles per read
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(the corresponding data rate is 12.8 MB/s)
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Write
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-----
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19.6 s
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19.7 s
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19.6 s
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average:
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19.6 s / 2^27 write cycles = 146.0 ns / write cycle
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which means 7.3 clock cycles per write
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(the corresponding data rate is 27.4 MB/s)
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Mix (75% read, 25% write)
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-------------------------
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36.2 s
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36.1 s
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36.2 s
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average:
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36.2 s / 2^27 operations = 269.7 ns / operation
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which means 13.5 clock cycles per operation
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Conclusions
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-----------
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1) The weighted average from read and write operations
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(0.75*15.6 + 0.25*7.3) is a very good approximation
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for the value measured in the "mixed" case. This
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confirms the different values for the "read" and
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"write" cases.
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2) The test circuit needs one clock cycle to recover
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from a read or write operation before the next one
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is started. The recommended number of clock cycles
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for a memory simulation are therefore
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read : 14 clock cycles
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write : 6 clock cycles
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measured from start of the operation (leading edge
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of signal stb) to end of the operation (trailing
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edge of signal ack).
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