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Line 1... |
//
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//
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// clk_rst.v -- clock and reset generator
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// clk_rst.v -- clock and reset generator
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//
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//
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module clk_rst(clk_in, reset_in,
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`timescale 1ns/10ps
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`default_nettype none
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module clk_rst(clk_in, rst_in,
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ddr_clk_0, ddr_clk_90, ddr_clk_180,
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ddr_clk_0, ddr_clk_90, ddr_clk_180,
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ddr_clk_270, ddr_clk_ok, clk, reset);
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ddr_clk_270, ddr_clk_ok, clk, rst);
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input clk_in;
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input clk_in;
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input reset_in;
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input rst_in;
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output ddr_clk_0;
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output ddr_clk_0;
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output ddr_clk_90;
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output ddr_clk_90;
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output ddr_clk_180;
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output ddr_clk_180;
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output ddr_clk_270;
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output ddr_clk_270;
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output ddr_clk_ok;
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output ddr_clk_ok;
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output clk;
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output clk;
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output reset;
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output rst;
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wire clk50_in;
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wire clk50_in;
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wire clk50_out;
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wire clk50_out;
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wire clk50_ok;
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wire clk50_ok;
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wire clk100_out;
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wire clk100_out;
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Line 29... |
wire clk100_90;
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wire clk100_90;
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wire clk100_180;
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wire clk100_180;
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wire clk100_270;
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wire clk100_270;
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wire clk100_ok;
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wire clk100_ok;
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reg reset_p;
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reg rst_p;
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reg reset_s;
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reg rst_s;
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reg [23:0] reset_counter;
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reg [23:0] rst_counter;
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wire reset_counting;
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wire rst_counting;
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//------------------------------------------------------------
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//------------------------------------------------------------
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IBUFG clk_in_buffer(
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IBUFG clk_in_buffer(
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.I(clk_in),
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.I(clk_in),
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Line 129... |
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assign ddr_clk_ok = clk100_ok;
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assign ddr_clk_ok = clk100_ok;
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//------------------------------------------------------------
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//------------------------------------------------------------
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assign reset_counting = (reset_counter == 24'hFFFFFF) ? 0 : 1;
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assign rst_counting = (rst_counter == 24'hFFFFFF) ? 0 : 1;
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always @(posedge clk) begin
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always @(posedge clk) begin
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reset_p <= reset_in;
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rst_p <= rst_in;
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reset_s <= reset_p;
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rst_s <= rst_p;
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if (reset_s | ~clk50_ok | ~clk100_ok) begin
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if (rst_s | ~clk50_ok | ~clk100_ok) begin
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reset_counter <= 24'h000000;
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rst_counter <= 24'h000000;
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end else begin
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end else begin
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if (reset_counting == 1) begin
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if (rst_counting == 1) begin
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reset_counter <= reset_counter + 1;
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rst_counter <= rst_counter + 1;
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end
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end
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end
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end
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end
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end
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assign reset = reset_counting;
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assign rst = rst_counting;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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