Subversion Repositories eco32

//

//

// spi.v -- SPI bus controller

// spi.v -- SPI bus controller

//

//

           dac_sample_l, dac_sample_r, dac_next,

           dac_sample_l, dac_sample_r, dac_next,

           spi_sck, spi_mosi,

           spi_sck, spi_mosi,

           dac_cs_n, dac_clr_n,

           dac_cs_n, dac_clr_n,

           amp_cs_n, amp_shdn,

           amp_cs_n, amp_shdn,

           ad_conv);

           ad_conv);

    // internal interface

    // internal interface

    input clk;

    input clk;

    input spi_en;

    input spi_en;

    // DAC controller interface

    // DAC controller interface

    input [15:0] dac_sample_l;

    input [15:0] dac_sample_l;

    input [15:0] dac_sample_r;

    input [15:0] dac_sample_r;

    output dac_next;

    output dac_next;

  //

  //

  reg [9:0] timing;

  reg [9:0] timing;

  always @(posedge clk) begin

  always @(posedge clk) begin

      timing <= 10'h0;

      timing <= 10'h0;

    end else begin

    end else begin

      if (spi_en == 1'b0 && timing == 10'h0) begin

      if (spi_en == 1'b0 && timing == 10'h0) begin

        // put SPI on hold in state 0 if disabled

        // put SPI on hold in state 0 if disabled

        timing <= timing;

        timing <= timing;

  wire dac_shift;

  wire dac_shift;

  assign dac_next = (timing[9:0] == 10'h001) ? 1 : 0;

  assign dac_next = (timing[9:0] == 10'h001) ? 1 : 0;

  always @(posedge clk) begin

  always @(posedge clk) begin

      dac_ld <= 1'b1;

      dac_ld <= 1'b1;

    end else begin

    end else begin

      if (timing[9:0] == 10'h001) begin

      if (timing[9:0] == 10'h001) begin

        dac_ld <= 1'b0;

        dac_ld <= 1'b0;

      end

      end

  end

  end

  assign dac_shift = spi_sck & ~dac_ld;

  assign dac_shift = spi_sck & ~dac_ld;

  always @(posedge clk) begin

  always @(posedge clk) begin

      dac_sr <= 48'h0;

      dac_sr <= 48'h0;

    end else begin

    end else begin

      if (dac_next) begin

      if (dac_next) begin

        dac_sr[47:44] <= 4'b0011;

        dac_sr[47:44] <= 4'b0011;

        dac_sr[43:40] <= 4'b0000;

        dac_sr[43:40] <= 4'b0000;

      end

      end

    end

    end

  end

  end

  assign dac_cs_n = dac_ld;

  assign dac_cs_n = dac_ld;

  //------------------------------------------------------------

  //------------------------------------------------------------

  //

  //

  // amplifier controller

  // amplifier controller

  //

  //

  assign amp_cs_n = 1;

  assign amp_cs_n = 1;

  //------------------------------------------------------------

  //------------------------------------------------------------

  //

  //

  // ADC controller

  // ADC controller