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[/] [eco32/] [trunk/] [fpga/] [mc/] [boards/] [xsa-xst-3/] [src/] [bio/] [bio.v] - Diff between revs 190 and 191

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Rev 190 Rev 191
Line 4... Line 4... 
 
 
 
 
 
 
 
 
module bio(clk, reset,
 
module bio(clk, reset,
 
           en, wr, addr,
 
           en, wr, addr,
 
           data_in, data_out,
 
           data_in, data_out,
 
           wt);
 
           wt,
 
 
 
           sw1_3_n, sw1_4_n,
 
 
 
           sw2_n, sw3_n);
 
    // internal interface
 
    // internal interface
 
    input clk;
 
    input clk;
 
    input reset;
 
    input reset;
 
    input en;
 
    input en;
 
    input wr;
 
    input wr;
 
    input addr;
 
    input addr;
 
    input [31:0] data_in;
 
    input [31:0] data_in;
 
    output [31:0] data_out;
 
    output [31:0] data_out;
 
    output wt;
 
    output wt;
 
    // external interface
 
    // external interface
 
 
 
    input sw1_3_n;
 
 
 
    input sw1_4_n;
 
 
 
    input sw2_n;
 
 
 
    input sw3_n;
 
 
 
 
 
  reg [31:0] bio_out;
 
  reg [31:0] bio_out;
 
  wire [31:0] bio_in;
 
  wire [31:0] bio_in;
 
 
 
 
 
 
 
  reg sw1_3_p_n;
 
 
 
  reg sw1_3_s_n;
 
 
 
  reg sw1_4_p_n;
 
 
 
  reg sw1_4_s_n;
 
 
 
  reg sw2_p_n;
 
 
 
  reg sw2_s_n;
 
 
 
  reg sw3_p_n;
 
 
 
  reg sw3_s_n;
 
 
 
 
 
  always @(posedge clk) begin
 
  always @(posedge clk) begin
 
    if (reset) begin
 
    if (reset) begin
 
      bio_out[31:0] <= 32'h0;
 
      bio_out[31:0] <= 32'h0;
 
    end else begin
 
    end else begin
 
      if (en & wr & ~addr) begin
 
      if (en & wr & ~addr) begin
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  assign data_out[31:0] =
 
  assign data_out[31:0] =
 
    (addr == 0) ? bio_out[31:0] : bio_in[31:0];
 
    (addr == 0) ? bio_out[31:0] : bio_in[31:0];
 
  assign wt = 0;
 
  assign wt = 0;
 
 
 
 
 
  assign bio_in[31:0] = { 28'h0, 4'h0 };
 
  always @(posedge clk) begin
 
 
 
    sw1_3_p_n <= sw1_3_n;
 
 
 
    sw1_3_s_n <= sw1_3_p_n;
 
 
 
    sw1_4_p_n <= sw1_4_n;
 
 
 
    sw1_4_s_n <= sw1_4_p_n;
 
 
 
    sw2_p_n <= sw2_n;
 
 
 
    sw2_s_n <= sw2_p_n;
 
 
 
    sw3_p_n <= sw3_n;
 
 
 
    sw3_s_n <= sw3_p_n;
 
 
 
  end
 
 
 
 
 
 
 
  assign bio_in[31:0] =
 
 
 
    { 28'h0, ~sw1_3_s_n, ~sw1_4_s_n, ~sw2_s_n, ~sw3_s_n };
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
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