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//
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//
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// clk_rst.v -- clock and reset generator
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// clk_rst.v -- clock and reset generator
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//
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//
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module clk_rst(clk_in, reset_inout_n,
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`timescale 1ns/10ps
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`default_nettype none
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module clk_rst(clk_in, rst_inout_n,
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sdram_clk, sdram_fb,
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sdram_clk, sdram_fb,
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clk, clk_ok, reset);
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clk, clk_ok, rst);
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input clk_in;
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input clk_in;
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inout reset_inout_n;
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inout rst_inout_n;
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output sdram_clk;
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output sdram_clk;
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input sdram_fb;
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input sdram_fb;
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output clk;
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output clk;
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output clk_ok;
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output clk_ok;
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output reset;
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output rst;
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wire clk_in_buf;
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wire clk_in_buf;
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wire int_clk;
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wire int_clk;
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wire int_locked;
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wire int_locked;
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wire ext_rst_n;
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wire ext_rst_n;
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wire ext_fb;
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wire ext_fb;
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wire ext_locked;
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wire ext_locked;
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reg reset_p_n;
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reg rst_p_n;
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reg reset_s_n;
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reg rst_s_n;
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reg [23:0] reset_counter;
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reg [23:0] rst_counter;
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wire reset_counting;
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wire rst_counting;
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//------------------------------------------------------------
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//------------------------------------------------------------
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IBUFG clk_in_buffer(
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IBUFG clk_in_buffer(
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.I(clk_in),
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.I(clk_in),
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assign clk_ok = int_locked & ext_locked;
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assign clk_ok = int_locked & ext_locked;
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//------------------------------------------------------------
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//------------------------------------------------------------
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assign reset_counting = (reset_counter == 24'hFFFFFF) ? 0 : 1;
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assign rst_counting = (rst_counter == 24'hFFFFFF) ? 0 : 1;
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assign reset_inout_n = (reset_counter[23] == 0) ? 1'b0 : 1'bz;
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assign rst_inout_n = (rst_counter[23] == 0) ? 1'b0 : 1'bz;
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always @(posedge clk_in_buf) begin
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always @(posedge clk_in_buf) begin
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reset_p_n <= reset_inout_n;
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rst_p_n <= rst_inout_n;
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reset_s_n <= reset_p_n;
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rst_s_n <= rst_p_n;
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if (reset_counting == 1) begin
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if (rst_counting) begin
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reset_counter <= reset_counter + 1;
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rst_counter <= rst_counter + 1;
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end else begin
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end else begin
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if (~reset_s_n | ~clk_ok) begin
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if (~rst_s_n | ~clk_ok) begin
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reset_counter <= 24'h000000;
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rst_counter <= 24'h000000;
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end
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end
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end
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end
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end
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end
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assign reset = reset_counting;
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assign rst = rst_counting;
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endmodule
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endmodule
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