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[/] [eco32/] [trunk/] [fpga/] [mc/] [boards/] [xsa-xst-3/] [src/] [dac/] [dac.v] - Diff between revs 288 and 290

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Rev 288	Rev 290
Line 1...	Line 1...
`//`	`//`
`// dac.v -- DAC control circuit`	`// dac.v -- DAC control circuit`
`//`	`//`


`module dac(clk, reset,`	`timescale 1ns/10ps
	`default_nettype none


	`module dac(clk, rst,`
`sample_l, sample_r, next,`	`sample_l, sample_r, next,`
`mclk, sclk, lrck, sdti);`	`mclk, sclk, lrck, sdti);`
`input clk;`	`input clk;`
`input reset;`	`input rst;`
`input [15:0] sample_l;`	`input [15:0] sample_l;`
`input [15:0] sample_r;`	`input [15:0] sample_r;`
`output next;`	`output next;`
`output mclk;`	`output mclk;`
`output sclk;`	`output sclk;`
Line 19...	Line 23...
`reg [9:0] timing;`	`reg [9:0] timing;`
`reg [63:0] sr;`	`reg [63:0] sr;`
`wire shift;`	`wire shift;`

`always @(posedge clk) begin`	`always @(posedge clk) begin`
`if (reset) begin`	`if (rst) begin`
`timing <= 10'h0;`	`timing <= 10'h0;`
`end else begin`	`end else begin`
`timing <= timing + 1;`	`timing <= timing + 1;`
`end`	`end`
`end`	`end`
Line 34...	Line 38...

`assign next = (timing[9:0] == 10'h1FF) ? 1 : 0;`	`assign next = (timing[9:0] == 10'h1FF) ? 1 : 0;`
`assign shift = (timing[3:0] == 4'hF) ? 1 : 0;`	`assign shift = (timing[3:0] == 4'hF) ? 1 : 0;`

`always @(posedge clk) begin`	`always @(posedge clk) begin`
`if (reset) begin`	`if (rst) begin`
`sr <= 64'h0;`	`sr <= 64'h0;`
`end else begin`	`end else begin`
`if (next) begin`	`if (next) begin`
`sr[63:52] <= 12'h000;`	`sr[63:52] <= 12'h000;`
`sr[51:32] <= { sample_l[15:0], 4'h0 };`	`sr[51:32] <= { sample_l[15:0], 4'h0 };`

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